System and method for router data aggregation and delivery
View Patent ↗A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There can be a random choice of available scrambler seeds for any particular chunk to avoid malicious forcing of zero and one patterns or run lengths of bit zeroes and ones. There are a chunk cyclical redundancy check (CRC) as well as forward error correction (FEC) bytes to detect and/or correct any errors and also to insure a high degree of data and control integrity. Advantageously, a framing symbol inserted into the chunk format itself allows the receiving circuitry to identify or locate a particular chunk format. “Break Bytes” and “Make Bytes” fields located at the beginning of a chunk preamble precondition an optical receiver to a proper state before the actual chunk arrives at the receiver.
1. A method for switching Internet Protocol (IP) packets, said method comprising:
constructing a container frame;
wherein the container frame contains a plurality of IP packets, each IP packet including a respective IP header and payload; and
wherein the container frame includes at least one of:
an error correction code; and
an error detection code;
including a framing symbol in the container frame, wherein the framing symbol locates beginning and trailing ends of the container; and
scrambling the bits in the container frame to balance a running run-length parity of the bits.
2. The method of claim 1 , wherein the framing symbol is adjacent to the trailing end of the container frame.
3. The method of claim 1 , further comprising determining the beginning and the trailing ends of the container frame based at least on the framing symbol.
4. The method of claim 1 , wherein the error correction code is a forward error correction (FEC) code.
5. The method of claim 1 , wherein the error detection code is a cyclical redundancy check (CRC) code.
6. The method of claim 1 , further comprising:
adding a header to the container frame.
7. The method of claim 6 , wherein the header indicates a type of the container frame.
8. The method of claim 6 , wherein the header includes a header parity.
9. The method of claim 6 , wherein the header includes a sequence number.
10. The method of claim 9 , further comprising:
performing error detection, correction, or both, using the sequence number in the header for alerting that the container frame is potentially corrupted.
11. The method of claim 1 , further comprising:
extracting the IP packets from the container frame.
12. A switch, comprising:
a switch fabric to switch a container frame, wherein the container frame includes a plurality of IP packets and a framing symbol, each IP packet including a respective IP header and payload;
wherein the container frame includes at least one of:
an error correction code, and
an error detection code;
wherein the framing symbol locates beginning and trailing ends of the container; and
wherein bits in the container frame are scrambled to balance a run-length parity of the bits.
13. The switch of claim 12 , wherein the framing symbol is located adjacent to the trailing end of the container frame.
14. The switch of claim 12 , wherein the error correction is an FEC code located adjacent to the framing symbol.
15. The switch of claim 12 , wherein the error detection is a CRC code located adjacent to the framing symbol.
16. The switch of claim 12 , wherein the container frame includes a header.
17. The switch of claim 16 , wherein the header identifies a type of the container frame.
18. The switch of claim 16 , wherein the header includes a header parity.
19. The switch of claim 16 , wherein the header identifies an input and an output of the switch fabric.
20. The switch of claim 12 , further comprising:
a first stage at an input side of the switch fabric and a second stage at an output side of the switch fabric,
wherein the first stage is configured to construct the container frame, and the second stage is configured to extract IP packets from the container frame.