Discharge digital-to-analog converter
View Patent ↗A digital-to-analog conversion circuit operates by selectively discharging members of a plurality of capacitors. Charging of the capacitors occurs during a reset period while digital-to-analog conversion occurs as the capacitors are discharged. Those capacitors that are discharged are selected from the plurality of capacitors based on a digital input. The analog output includes the charge discharged from the capacitors. The capacitors are optionally divided into separate capacitor banks.
1. A digital-to-analog converter comprising:
a plurality of capacitors;
one or more voltage sources configured for recharging the plurality of capacitors;
a plurality of recharge switches disposed between the one or more voltage sources and the plurality of capacitors, each of the plurality of recharge switches being configured to control recharging of one of the plurality of capacitors, respectively;
a plurality of discharge switches each respectively configured to discharge one of the plurality of capacitors to produce a differential analog output; and
a control circuit configured to select which of the plurality of capacitors to charge and discharge using one or more of the plurality of discharge switches or one or more of the plurality of recharge switches, the selection being based on the value of a digital input and the analog output including a pulse of charge representative of the digital input, wherein members of the plurality of capacitors are disposed in different unit cells configured to be operated in series such that one member of the plurality of capacitors is charged while another member of the plurality of capacitors is being discharged.
2. The digital-to-analog converter of claim 1 , wherein each of the plurality of capacitors has different capacitances or are charged to different voltages.
3. The digital-to-analog converter of claim 1 , wherein the control circuit is configured to produce the analog output
at a frequency greater than a frequency of the digital input, and the analog output is a mix of the digital input and a sampling frequency.
4. The digital-to-analog converter of claim 1 , wherein the plurality of capacitors are distributed among a plurality of capacitor banks.
5. The digital-to-analog converter of claim 4 , wherein one of the plurality of capacitor banks is in a thermometer configuration and one of the plurality of capacitor banks is in a binary configuration.
6. The digital-to-analog converter of claim 1 , wherein the control circuit is configured to selected which of the plurality of capacitors to charge by closing a subset of the plurality of recharge switches.
7. The digital-to-analog converter of claim 1 , wherein the control circuit is configured to select which of the plurality of capacitors to discharge by closing a subset of the plurality of discharge switches.
8. The digital-to-analog converter of claim 1 , further comprising an output circuit configured for storage of charge discharged from the plurality of capacitors prior to providing this charge as the analog output.
9. The digital-to-analog converter of claim 8 , wherein the output circuit includes a storage capacitor separated from the plurality of capacitors by the plurality of discharge switches and configured to receive charge from the plurality of capacitors.
10. The digital-to-analog converter of claim 8 , wherein the output circuit includes a output switch configured to allow redistribution of charge among the plurality of capacitors prior to producing the analog output.
11. A digital-to-analog converter comprising:
a first capacitor of a first cell unit;
a second capacitor of a second cell unit;
one or more voltage sources configured to charge the first capacitor and the second capacitors;
a first recharge switch disposed between the first capacitor and the one or more voltage sources;
a second recharge switch disposed between the second capacitor and the one or more voltage sources;
a first discharge switch configured to discharge the first capacitor;
a second discharge switch configured to discharge the second capacitor; and
an output circuit configured to receive the discharge of the first capacitor through the first discharge switch, to receive the discharge of the second capacitor through the second discharge switch, and to provide a combination of charge discharged from the first capacitor and charge discharged from the second capacitor as an analog output pulse of the digital-to analog converter;
wherein the first capacitor and the second capacitor are configured to be operated in series such that the first capacitor is charged while the second capacitor is being discharged.
12. The digital-to-analog converter of claim 11 , wherein the output circuit is further configured to receive the discharge of the first capacitor and the discharge of the second capacitor as at least part of a differential signal.
13. The digital-to-analog converter of claim 11 , wherein states of the first and second discharge switch are responsive to a value of a digital input.
14. The digital-to-analog converter of claim 11 , wherein states of the first and second recharge switches are responsive to a value of a digital input switch.
15. The digital-to-analog converter of claim 11 , wherein the output circuit includes an output switch configured to allow redistribution of charge between the first capacitor and the second capacitor.
16. The digital-to-analog converter of claim 11 , wherein the output circuit includes a storage capacitor configured to receive the charge from the first capacitor and the second capacitor via the first discharge switch and the second discharge switch, respectively, and an output switch configured to control delivery of the combined charge from the storage capacitor.
17. The digital-to-analog converter of claim 11 , further comprising a control circuit configured to maintain the first and second recharge switches in a closed state while maintaining the first and second recharge switches in an open state while maintaining a subset of the first and second discharge switches in a close state during a conversion period.
18. The digital-to-analog converter of claim 11 , wherein the control circuit is configured to generate an output signal at a frequency within a sideband resulting from a mixture of a frequency of the multi-bit digital input and a sampling frequency of the analog to digital digital-to-analog converter.