SRAM macro test flop
A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.
1. A SRAM (Static Random Access Memory) macro test flop circuit, driven by a source clock signal, comprising:
a flip-flop circuit comprising:
a master latch circuit comprising:
a master feed-back circuit comprising a master storage node, and
a master feed-forward circuit, wherein the master feed-forward circuit provides a control signal for writing to the master storage node, and
a slave latch circuit comprising:
a slave feed-back circuit comprising a slave storage node, and
a slave feed-forward circuit operatively driven from the master latch, wherein the slave feed-forward circuit provides a control signal for writing to the slave storage node,
a scan control circuit comprising:
a scan slave feed-forward circuit providing a control signal for writing a scan data to the slave storage node,
a scan latch circuit comprising:
a scan feed-back circuit comprising a scan storage node,
a scan feed-forward circuit operatively driven from the slave latch, wherein the scan feed-forward circuit provides a control signal for writing to the scan storage node, and
a scan driver, with a scan output port, operatively driven by the scan feed-back circuit, and
a scan master feed-forward circuit operatively driven from the scan latch, wherein the scan master feed-forward circuit provides a control signal for writing to the master storage node, and
an output buffer circuit comprising:
a master driver, with a master output port, operatively driven from the master latch, and
a slave driver, with a slave output port, operatively driven from the slave latch.
2. The SRAM macro test flop circuit of claim 1 , wherein a single polarity of the source clock signal is used in the SRAM macro test flop circuit.
3. The SRAM macro test flop circuit of claim 1 , wherein the source clock signal is forced to a high logic state during writing scan data to the master storage node.
4. The SRAM macro test flop circuit of claim 1 , the master feed-forward circuit comprising: a two to one multiplexer with first data-in and second data-in as two multiplexer inputs, wherein multiplexer output provides a control signal for writing to the master storage node.
5. The SRAM macro test flop circuit of claim 4 , wherein the first data-in is operatively driven from user data.
6. The SRAM macro test flop circuit of claim 4 , wherein the second data-in is operatively driven from the scan output port.
7. A semiconductor device comprising:
a mechanical package; and
a semiconductor die comprising:
a semiconductor layer,
a plurality of metal layers,
a clock distribution network that distributes a clock signal within the die, and
a SRAM (Static Random Access Memory) macro test flop circuit, driven by a source clock signal, comprising:
a flip-flop circuit comprising:
a master latch circuit comprising:
a master feed-back circuit comprising a master storage node, and
a master feed-forward circuit, wherein the master feed-forward circuit provides a control signal for writing to the master storage node, and
a slave latch circuit comprising:
a slave feed-back circuit comprising a slave storage node, and
a slave feed-forward circuit operatively driven from the master latch, wherein the slave feed-forward circuit provides a control signal for writing to the slave storage node,
a scan control circuit comprising:
a scan slave feed-forward circuit providing a control signal for writing a scan data to the slave storage node,
a scan latch circuit comprising:
a scan feed-back circuit comprising a scan storage node,
a scan feed-forward circuit operatively driven from the slave latch, wherein the scan feed-forward circuit provides a control signal for writing to the scan storage node, and
a scan driver, with a scan output port, operatively driven by the scan feed-back circuit, and
a scan master feed-forward circuit operatively driven from the scan latch, wherein the scan master feed-forward circuit provides a control signal for writing to the master storage node, and
an output buffer circuit comprising:
a master driver, with a master output port, operatively driven from the master latch, and
a slave driver, with a slave output port, operatively driven from the slave latch.
8. The semiconductor device of claim 7 , wherein a single polarity of the source clock signal is used in the SRAM macro test flop circuit.
9. The semiconductor device of claim 7 , wherein the source clock signal is forced to a high logic state during writing scan data to the master storage node.
10. The semiconductor device of claim 7 , the master feed-forward circuit comprising: a two to one multiplexer with first data-in and second data-in as two multiplexer inputs, wherein multiplexer output provides a control signal for writing to the master storage node.
11. The semiconductor device of claim 10 , wherein the first data-in is operatively driven from user data.
12. The semiconductor device of claim 10 , wherein the second data-in is operatively driven from the scan output port.
13. A system comprising:
an input device;
an output device;
a mechanical chassis;
a printed circuit board; and
a semiconductor device comprising:
a mechanical package; and
a semiconductor die comprising:
a semiconductor layer,
a plurality of metal layers,
a clock distribution network that distributes a clock signal within the die, and
a SRAM (Static Random Access Memory) macro test flop circuit, driven by a source clock signal, comprising:
a flip-flop circuit comprising:
a master latch circuit comprising:
a master feed-back circuit comprising a master storage node, and
a master feed-forward circuit, wherein the master feed-forward circuit provides a control signal for writing to the master storage node, and
a slave latch circuit comprising:
a slave feed-back circuit comprising a slave storage node, and
a slave feed-forward circuit operatively driven from the master latch, wherein the slave feed-forward circuit provides a control signal for writing to the slave storage node,
a scan control circuit comprising:
a scan slave feed-forward circuit providing a control signal for writing a scan data to the slave storage node,
a scan latch circuit comprising:
a scan feed-back circuit comprising a scan storage node, a scan feed-forward circuit operatively driven from the slave latch, wherein the scan feed-forward circuit provides a control signal for writing to the scan storage node, and
a scan driver, with a scan output port, operatively driven by the scan feed-back circuit, and
a scan master feed-forward circuit operatively driven from the scan latch, wherein the scan master feed-forward circuit provides a control signal for writing to the master storage node, and
an output buffer circuit comprising:
a master driver, with a master output port, operatively driven from the master latch, and
a slave driver, with a slave output port, operatively driven from the slave latch.
14. The system of claim 13 , wherein a single polarity of the source clock signal is used in the SRAM macro test flop circuit.
15. The system of claim 13 , wherein the source clock signal is forced to a high logic state during writing scan data to the master storage node.
16. The system of claim 13 , the master feed-forward circuit comprising: a two to one multiplexer with first data-in and second data-in as two multiplexer inputs, wherein multiplexer output provides a control signal for writing to the master storage node.
17. The system of claim 16 , wherein the second data-in is operatively driven from the scan output port.