IP Library Granted Patent US 8,017,465
Granted Patent B2
US 8,017,465 · App. 12/565,953 · Granted Sep 13, 2011

Method for manufacturing array substrate of liquid crystal display

Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
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Quick Facts
Patent No.
US 8,017,465
App. No.
12/565,953
Granted
Sep 13, 2011
Kind
B2
Abstract

A method for manufacturing an array substrate of liquid crystal display is performed with the following steps: providing a substrate having gate lines, a gate insulating layer and an active layer pattern formed thereon in this order; depositing a first transparent conductive layer and a source/drain metal layer in this order on the substrate; forming a photoresist layer on the source/drain metal layer through a triple-tone mask; performing a wet-etching process on the source/drain metal layer and the first transparent conductive layer exposed from the photoresist layer; performing a first ashing process on the photoresist layer and performing a dry-etching process on the source/drain metal layer, the first transparent conductive layer and the active layer pattern exposed by the first ashing process; performing a second ashing process on the photoresist layer and performing a wet-etching process on the source/drain metal layer exposed by the second ashing process; and removing the remaining photoresist layer. According to the invention, the over-etching on the TFT channel region can be reduced and the display quality of the liquid crystal display can be ensured.

Claims (32)

1. A method for manufacturing an array substrate of liquid crystal display, comprising:

a. providing a substrate having a gate line, a gate insulating layer and an active layer pattern formed thereon in this order;

b. depositing a first transparent conductive layer and a source/drain metal layer in this order on the substrate;

c. forming a photoresist pattern layer on the source/drain metal layer through a triple-tone mask;

d. performing a wet-etching process on the source/drain metal layer and the first transparent conductive layer exposed from the photoresist pattern layer;

e. performing a first ashing process on the photoresist pattern layer and performing a dry-etching process on the source/drain metal layer, the first transparent conductive layer and the active layer pattern exposed by the first ashing process;

f. performing a second ashing process on the photoresist pattern layer and performing a wet-etching process on the source/drain metal layer exposed by the second ashing process; and

g. removing the remaining photoresist pattern layer.

2. The method for manufacturing the array substrate of liquid crystal display according to claim 1 , wherein for the photoresist pattern layer formed through the triple-tone mask, the thickness of the region to be exposed by the first ashing process of the step e is thinner than that of the region to be exposed by the second ashing process of the step f, and the thickness of the region to be exposed by the second ashing process of the step f is thinner than the thickness of the region corresponding to the remaining region of the step g.

3. The method for manufacturing the array substrate of liquid crystal display according to claim 2 , further comprising:

h. depositing an insulating layer on the substrate after the step g and forming a passivation layer pattern and via holes by a photolithographic process.

4. The method for manufacturing the array substrate of liquid crystal display according to claim 3 , further comprising:

i. depositing a second transparent conductive layer on the substrate after the step h and forming a common electrode from the second transparent conductive layer by a photolithographic process.

5. The method for manufacturing the array substrate of liquid crystal display according to claim 2 , further comprises comprising:

j. depositing an insulating layer on the substrate after the step g, forming a passivation layer pattern and via holes by a photolithographic process using a photoresist without removing the photoresist, depositing a second transparent conductive layer on the photoresist and the passivation layer pattern, and forming a common electrode from the second transparent conductive layer on the passivation layer pattern using a lift-off process by removing the second transparent conductive layer on the photoresist.

6. A method for manufacturing an array substrate of liquid crystal display, comprising:

aa. providing a substrate having a first metal layer, a first insulating layer, a semiconductor layer and a doped semiconductor layer formed on a thin film transistor (TFT) region, wherein the substrate is covered by the first insulating layer, the substrate comprises a pixel region, a non-display region and a TFT region, and the TFT region comprises a TFT channel region, a source electrode region and a drain electrode region;

bb. depositing a first transparent conductive layer and a second metal layer in this order on the substrate after the step aa;

cc. forming a photoresist pattern layer on the second metal layer through a triple-tone mask, wherein the photoresist pattern layer in the TFT channel region has a first thickness, the photoresist pattern layer in the pixel region has a second thickness, the photoresist pattern layer in the source electrode region and the drain electrode region has a third thickness, and the first thickness is smaller than the second thickness while the second thickness is smaller than the third thickness;

dd. etching the second metal layer and the first transparent conductive layer in the non-display region;

ee. performing a first ashing process on the photoresist pattern layer to expose the second metal layer in the TFT channel region;

ff. etching the second metal layer, the first transparent conductive layer and the doped semiconductor layer in the TFT channel region;

gg. performing a second ashing process on the photoresist pattern layer to expose the second metal layer in the pixel region;

hh. etching the second metal layer in the pixel region; and

ii. removing the remaining photoresist pattern layer.

7. The method for manufacturing the array substrate of liquid crystal display according to claim 6 , wherein a wet-etching process is employed in the step dd and the step hh, and a dry-etching process is employed in the step ff.

8. The method for manufacturing the array substrate of liquid crystal display according to claim 7 , wherein the method further comprises the following step:

jj. depositing a second insulating layer on the substrate after the step ii and forming a passivation layer pattern and via holes by a photolithographic process.

9. The method for manufacturing the array substrate of liquid crystal display according to claim 8 , wherein the method further comprises the following step:

kk. depositing a second transparent conductive layer on the substrate after the step jj and forming a common electrode from the second transparent conductive layer by a photolithographic process.

10. The method for manufacturing the array substrate of liquid crystal display according to claim 7 , wherein the method further comprises the following step:

ll. depositing a second insulating layer on the substrate after the step ii, forming a passivation layer pattern and via holes by a photolithographic process using a photoresist without removing the photoresist, depositing a second transparent conductive layer on the photoresist and the passivation layer pattern, and forming a common electrode from the second transparent conductive layer on the passivation layer pattern using a lift-off process by removing the second transparent conductive layer on the photoresist.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2015
From: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD
To: BOE TECHNOLOGY GROUP CO., LTD.; BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO. LTD
Reel/Frame 036644/0601 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2009
From: CHOI, SEUNGJIN; SONG, YOUNGSUK; YOO, SEONGYEOL
To: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 023277/0722 →
Priority Claims (1)
CN 2008 1 0222792 · Sep 25, 2008 · national
Continuity (1)
Related Publication 20100075450A1 · Mar 25, 2010