IP Library Granted Patent US 8,003,518
Granted Patent B2
US 8,003,518 · App. 12/566,016 · Granted Aug 23, 2011

Semiconductor device fabrication method

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Quick Facts
Patent No.
US 8,003,518
App. No.
12/566,016
Granted
Aug 23, 2011
Kind
B2
Abstract

A semiconductor device fabrication method including the steps of: forming an interlayer insulating film on a substrate; forming an opening in the interlayer insulating film; forming an alloy layer containing manganese and copper to cover the inner surface of the opening; forming a first copper layer of a material containing primarily copper on the alloy layer to fill the opening; forming, on the first copper layer, a second copper layer of a material containing primarily copper and a higher concentration of oxygen, carbon or nitrogen than the first copper layer; heating the substrate on which the second copper layer has been formed; and removing the second copper layer.

Claims (33)

1. A semiconductor device fabrication method, comprising:

forming an interlayer insulating film on a substrate;

forming an opening in the interlayer insulating film;

forming an alloy layer containing manganese and copper to cover the inner surface of the opening;

forming a first copper layer of a material containing primarily copper on the alloy layer to fill the opening;

forming, on the first copper layer, a second copper layer of a material containing primarily copper and a higher concentration of oxygen, carbon or nitrogen than the first copper layer;

heating the substrate on which the second copper layer has been formed; and

removing the second copper layer.

2. The semiconductor device fabrication method according to claim 1 , wherein the first copper layer is formed by electroplating using the alloy layer as a seed layer.

3. The semiconductor device fabrication method according to claim 1 , wherein the first and second copper layers are formed by electroplating; and

the electroplating of the second copper layer is performed at a lower current density than that of the electroplating of the first copper layer.

4. The semiconductor device fabrication method according to claim 1 , wherein the second copper layer is formed by chemical vapor deposition using a copper organic compound.

5. The semiconductor device fabrication method according to claim 1 , wherein the second copper layer is formed by chemical vapor deposition using Trimethylvinylsilyl hexafluoroacetylacetonate Cu (I) as a source.

6. The semiconductor device fabrication method according to claim 1 , wherein the second copper layer is formed by sputtering.

7. The semiconductor device fabrication method according to claim 6 , wherein the sputtering is performed in an introduced gas containing oxygen, carbon or nitrogen.

8. The semiconductor device fabrication method according to claim 1 , wherein the interlayer insulating film contains silicon and oxygen; and in the step of heating the substrate, a barrier film containing primarily MnSi X O Y is formed inside the opening.

9. The semiconductor device fabrication method according to claim 8 , wherein in the step of heating the substrate, the substrate is heated at a temperature in the range from 250° C. to 400° C. inclusive.

10. The semiconductor device fabrication method according to claim 8 , wherein in the step of heating the substrate, the substrate is heated in an atmosphere of a hydrogen gas, a nitrogen gas, or a argon gas.

11. The semiconductor device fabrication method according to claim 1 , wherein the alloy layer is formed by sputtering.

12. The semiconductor device fabrication method according to claim 1 , wherein the alloy layer contains 0.1 to 10 atom percent of manganese.

13. The semiconductor device fabrication method according to claim 1 , wherein the opening is formed on an interconnect.

14. The semiconductor device fabrication method according to claim 13 , wherein the interconnect is made of a material containing primarily copper and a surface oxide is removed from the interconnect prior to the formation of the alloy layer.

15. The semiconductor device fabrication method according to claim 13 , wherein a barrier film of a material containing primarily tantalum or tantalum nitride is formed between the interconnect and the interlayer insulating film.

16. A semiconductor device fabrication method, comprising:

forming an interlayer insulating film on a substrate;

forming an opening in the interlayer insulating film;

forming an alloy layer containing manganese and copper to cover the inner surface of the opening;

forming a first copper layer of a material containing primarily copper on the alloy layer to fill the opening;

introducing oxygen, carbon or nitrogen into a surface of the first copper layer;

after the step of introducing, heating the substrate on which the first copper layer has been formed; and

after the step of heating, removing a portion of the first copper layer that is outside the opening.

17. The semiconductor device fabrication method according to claim 16 , wherein in the step of introducing oxygen, carbon or nitrogen, ions of oxygen, carbon or nitrogen are implanted into the surface of the first copper layer to introduce the oxygen, carbon, or nitrogen.

18. The semiconductor device fabrication method according to claim 16 , wherein in the step of introducing oxygen, carbon or nitrogen, the oxygen, carbon or nitrogen is introduced by heating the substrate while the substrate is exposed to a carbon monoxide gas, a carbon dioxide gas, an oxygen gas, a nitrogen gas, or a nitrogen dioxide gas.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2009
From: HANEDA, MASAKI; SHIMIZU, NORIYOSHI; SUNAYAMA, MICHIE
To: FUJITSU MICROELCTRONICS LIMITED
Reel/Frame 023280/0327 →