Semiconductor device and method of manufacturing the semiconductor device

1. A semiconductor device comprising:

a transistor configuration including first and second gate electrodes on a semiconductor substrate, the first gate electrode having at least a first bottom layer and a first upper layer including polycrystalline silicon grains, the second gate electrode having at least a second bottom layer and a second bottom layer including polycrystalline silicon grains;

wherein the first gate electrode is an nMOS gate electrode formed in an nMOS region of the transistor configuration, and the second gate electrode is a pMOS gate electrode formed in a pMOS region of the transistor configuration;

wherein the polycrystalline silicon grains included in the first bottom layer have a greater particle diameter than the polycrystalline grains included in the first upper layer and cause volume expansion of the first bottom layer;

wherein the volume expansion of the first bottom layer generates a compressive stress that causes the first bottom layer to apply compressive stress to a first channel region,

wherein the first channel region is located immediately below the first gate electrode, the compressive stress existing in the first channel region is in a direction vertical to a surface of the semiconductor substrate,

wherein the polycrystalline grains included in the first bottom layer have a greater particle diameter than the polycrystalline grains included in the second bottom layer.

2. The semiconductor device as claimed in claim 1 , wherein the polycrystalline silicon grains included in the first bottom layer have a greater particle diameter than the polycrystalline grains included in the second upper layer.

3. The semiconductor device as claimed in claim 1 , wherein the first bottom layer of the first gate electrode contains an impurity including at least one of P, Ge, and Si.

4. The semiconductor device as claimed in claim 1 , wherein the second gate electrode contains an impurity.

5. The semiconductor device as claimed in claim 1 , wherein the pMOS region includes a buried SiGe layer.

6. The semiconductor device as claimed in claim 1 , wherein the first upper and bottom layers of the first gate electrode have the same thicknesses as the thicknesses of the second upper and bottom layers of the second gate electrode.

7. The semiconductor device as claimed in claim 1 ,

wherein the each of the first and the second gate electrodes has a sidewall spacer,

wherein the sidewall spacer has a double-layer configuration that maintains a lattice strain caused by the compressive stress applied to the first channel region, and

wherein the double-layer configuration includes a first insulation film and a second insulation film formed on an outer side of the first insulation film.

8. The semiconductor device as claimed in claim 1 ,

wherein the each of the first and the second gate electrodes has a sidewall spacer,

wherein the sidewall spacer has a double-layer configuration that maintains a lattice strain caused by the compressive stress applied to the first channel region,

wherein the double-layer configuration includes a first insulation film and a second insulation film formed on an outer side of the first insulation film, and

wherein the first insulation film is a silicon oxide film and the second insulation film is a silicon nitride film.

9. The semiconductor device as claimed in claim 1 ,

wherein the compressive stress in the first channel region is larger than a compressive stress in a second channel region located immediately below the second gate electrode.

10. The semiconductor device as claimed in claim 1 ,

wherein dopants doped in the first bottom layer differ from dopants doped in the second bottom layer.