Generating a hardware description for a programmable hardware element based on a graphical program including multiple models of computation

1. A non-transitory computer-accessible memory medium storing program instructions, wherein the program instructions are executable by a computer system to:

display a graphical program, wherein the graphical program comprises a first portion including a first plurality of interconnected nodes that visually indicates functionality of the first portion of the graphical program and operates according to a first computational model, and wherein the graphical program further comprises a second portion including a second plurality of interconnected nodes that visually indicates functionality of the second portion of the graphical program and operates according to a second computational model that is different than the first computational model, wherein the first portion of the graphical program includes a structure that has an interior region, wherein the second portion of the graphical program including the second plurality of interconnected nodes is displayed within the interior region of the structure; and

generate a hardware description based on the graphical program, wherein the hardware description describes a hardware implementation of the graphical program, and wherein the hardware description is configured to configure a programmable hardware element to implement functionality of the graphical program.

2. The memory medium of claim 1 , wherein the first computational model comprises data flow, and wherein the second computational model comprises one or more of:

state flow;

time-based simulation flow;

synchronous reactive;

process network;

execution flow; or

physical simulation.

3. The memory medium of claim 1 ,

wherein the hardware description comprises a first portion corresponding to the first portion of the graphical program;

wherein the hardware description comprises a second portion corresponding to the second portion of the graphical program;

wherein the hardware description specifies communication between the first portion and the second portion.

4. The memory medium of claim 1 , wherein the program instructions are further executable by the computer system to:

configure the programmable hardware element using the hardware description, wherein, during execution, the programmable hardware element performs the functionality of the graphical program.

5. The memory medium of claim 1 ,

wherein the first portion and the second portion of the graphical program are included in a same graphical interface.

6. The memory medium of claim 1 , wherein the programmable hardware element is comprised in a real time target.

7. The memory medium of claim 1 ,

wherein the first computational model comprises a data flow computational model; and

wherein the second computational model comprises a state flow computational model.

8. The memory medium of claim 1 ,

wherein the first computational model comprises a data flow computational model; and

wherein the second computational model comprises a time-based simulation flow computational model.

9. The memory medium of claim 1 ,

wherein the first computational model comprises a data flow computational model; and

wherein the second computational model comprises a synchronous reactive computational model.

10. The memory medium of claim 1 ,

wherein the first computational model comprises a data flow computational model; and

wherein the second computational model comprises a physical simulation computational model.

11. The memory medium of claim 1 ,

wherein the first computational model comprises a time-based simulation flow computational model; and

wherein the second computational model comprises a state flow computational model.

12. A method, comprising:

displaying a graphical program on a computer system, wherein the graphical program comprises a first portion including a first plurality of interconnected nodes that visually indicates functionality of the first portion of the graphical program and operates according to a first computational model, and wherein the graphical program further comprises a second portion including a second plurality of interconnected nodes that visually indicates functionality of the second portion of the graphical program and operates according to a second computational model that is different than the first computational model, wherein the first portion of the graphical program includes a structure that has an interior region, wherein the second portion of the graphical program including the second plurality of interconnected nodes is displayed within the interior region of the structure; and

generating a hardware description based on the graphical program by the computer system, wherein the hardware description describes a hardware implementation of the graphical program, and wherein the hardware description is configured to configure a programmable hardware element to implement functionality of the graphical program.

13. The method of claim 12 , wherein the first computational model comprises data flow, and wherein the second computational model comprises one or more of:

state flow;

time-based simulation flow;

synchronous reactive;

process network;

execution flow; or

physical simulation.

14. The method of claim 12 ,

wherein the hardware description comprises a first portion corresponding to the first portion of the graphical program;

wherein the hardware description comprises a second portion corresponding to the second portion of the graphical program;

wherein the hardware description specifies communication between the first portion and the second portion.

15. The method of claim 12 , further comprising:

configuring the programmable hardware element using the hardware description, wherein, during execution, the programmable hardware element performs the functionality of the graphical program.

16. The method of claim 12 ,

wherein the first portion and the second portion of the graphical program are included in a same graphical interface.

17. The method of claim 12 , wherein the programmable hardware element is comprised in a real time target.

18. A system, comprising:

one or more processors; and

a memory medium coupled to the one or more processors, wherein the memory medium stores program instructions executable by the one or more processors to:

display a graphical program, wherein the graphical program comprises a first portion including a first plurality of interconnected nodes that visually indicates functionality of the first portion of the graphical program and operates according to a first computational model, and wherein the graphical program further comprises a second portion including a second plurality of interconnected nodes that visually indicates functionality of the second portion of the graphical program and operates according to a second computational model that is different than the first computational model, wherein the first portion of the graphical program includes a structure that has an interior region, wherein the second portion of the graphical program including the second plurality of interconnected nodes is displayed within the interior region of the structure; and

generate a hardware description based on the graphical program, wherein the hardware description describes a hardware implementation of the graphical program, and wherein the hardware description is configured to configure a programmable hardware element to implement functionality of the graphical program.

19. The system of claim 18 , wherein the first computational model comprises data flow, and wherein the second computational model comprises one or more of:

state flow;

time-based simulation flow;

synchronous reactive;

process network;

execution flow; or

physical simulation.

20. The system of claim 18 ,

wherein the hardware description comprises a first portion corresponding to the first portion of the graphical program;

wherein the hardware description comprises a second portion corresponding to the second portion of the graphical program;

wherein the hardware description specifies communication between the first portion and the second portion.

21. The system of claim 18 , wherein the program instructions are further executable to:

configure the programmable hardware element using the hardware description, wherein, during execution, the programmable hardware element performs the functionality of the graphical program.

22. The system of claim 18 ,

wherein the first portion and the second portion of the graphical program are included in a same graphical interface.