IP Library Granted Patent US 8,137,148
Granted Patent B2
US 8,137,148 · App. 12/570,024 · Granted Mar 20, 2012

Method of manufacturing monolithic parallel interconnect structure

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Quick Facts
Patent No.
US 8,137,148
App. No.
12/570,024
Granted
Mar 20, 2012
Kind
B2
Abstract

An optoelectronic device having a monolithic interconnect structure includes a continuous anode layer, a discontinuous cathode layer, and an electroactive layer sandwiched between the continuous anode layer and the discontinuous cathode layer.

Claims (15)

1. A process for fabricating an optoelectronic device, said process comprising: conveying a web comprising a continuous unpatternted anode layer through a roll to roll apparatus while forming a patterned electroactive layer on the continuous unpatterned anode layer; and forming a patterned cathode layer on the electroactive layer; wherein portions of the electroactive layer are selectively removed in a direction parallel the direction of the web transport; and the cathode layer is deposited solely on portions of the electroactive layer remaining after selectively removing portions thereof without stopping to form a cross-web pattern.

2. A process according to claim 1 , additionally comprising forming a plurality of electrical connections to the continuous unpatterned anode layer;

wherein at least one of the plurality of electrical connections passes through one of the plurality of vias.

3. A process according to claim 1 , wherein the step of forming a patterned electroactive layer on the continuous unpatterned anode layer comprises:

depositing an electroactive layer on the continuous unpatterned anode layer; and

selectively removing portions of the electroactive layer.

4. A process according to claim 1 , wherein an anode bus layer is deposited simultaneously with the cathode layer solely on exposed areas of the anode.

5. A process according to either of claim 1 , additionally comprising

forming a feedthrough layer comprising at least one feedthrough aperture to the discontinuous cathode; and

disposing at least one conductive patch electrically coupled to the continuous anode across at least one feedthrough aperture.

6. A process according to claim 1 , additionally comprising disposing an insulating layer on the discontinuous cathode layer, disposing a conducting layer on the insulating layer, and electrically coupling the conducting layer to the continuous anode layer.

7. A process according to claim 1 , additionally comprising disposing a plurality of areas of conducting material directly on the anode layer, electrically isolated from the cathode layer, and electrically coupled to the anode layer.

8. A process according to claim 1 , wherein the patterned cathode layer is configured in a plurality of ribbon-like structures.

9. A process according to claim 1 , additionally comprising disposing at least one anode bus region directly on a portion of the continuous unpatterned anode layer.

10. A process according to claim 1 , wherein the optoelectronic device is an organic light emitting device.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2016
From: GENERAL ELECTRIC COMPANY
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 038490/0022 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2016
From: GENERAL ELECTRIC COMPANY
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 038439/0315 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2009
From: FARQUHAR, DONALD SETON; DUGGAL, ANIL RAJ; HERZOG, MICHAEL SCOTT; YOUMANS, JEFFREY MICHAEL; RAKUFF, STEFAN; BOYD, LINDA ANN
To: GENERAL ELECTRIC COMPANY
Reel/Frame 023303/0290 →