Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading
View Patent ↗Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading. A novel approach is presented by which adjustable amplification and equalizer may be achieved using a C3MOS wideband data stage. This may be referred to as a C3MOS wideband data amplifier/equalizer circuit. This employs a wideband differential transistor pair that is fed using two separate transistor current sources. A switchable RC network is communicatively coupled between the sources of the individual transistors of the wideband differential transistor pair. There are a variety of means by which the switchable RC network may be implemented, including using a plurality of components (e.g., capacitors and resistors connected in parallel). In such an embodiment, each component may have an individual switch to govern its connectivity in the switchable RC network thereby allowing a broad range of amplification and equalization to be performed.
1. A circuit, comprising:
a first differential transistor that includes a first source;
a second differential transistor that includes a second source;
a first current source that is connected to the first source;
a second current source that is connected to the second source; and
a switchable RC network, that includes a plurality of switches such that at least one of the plurality of switches, a resistor, and a capacitor are connected in parallel, that is connected between the first source and the second source; and wherein:
the plurality of switches being operative either to short the first source to the second source or to select at least one of a resistance and a capacitance of the switchable RC network.
2. The circuit of claim 1 , wherein:
a first terminal of the first current source is connected to the first source;
a second terminal of the first current source is grounded;
a first terminal of the second current source is connected to the second source; and
a second terminal of the second current source is grounded.
3. The circuit of claim 1 , wherein:
the switchable RC network is operative to short the first source to the second source when the at least one of the plurality of switches connected in parallel with the resistor and the capacitor is closed.
4. The circuit of claim 1 , wherein:
the switchable RC network is operative to select an impedance from a plurality of impedances; and
the selected impedance is connected between the first source and the second source.
5. The circuit of claim 4 , wherein:
the selected impedance controls, at least in part, a gain and frequency response of the circuit.
6. The circuit of claim 1 , wherein:
the first differential transistor also includes a first gate; and
the second differential transistor also includes a second gate; and further comprising:
a first input impedance that is connected to a first differential input of the circuit and to the first gate; and
a second input impedance that is connected to a second differential input of circuit and to the second gate.
7. The circuit of claim 1 , wherein:
the first differential transistor also includes a first drain; and
the second differential transistor also includes a second drain; and further comprising:
a first output impedance that is connected to the first drain and to a supply voltage; and
a second output impedance that is connected to the second drain and to the supply voltage.
8. The circuit of claim 1 , wherein:
the first differential transistor also includes a first gate and a first drain; and
the second differential transistor also includes a second gate and a second drain; and further comprising:
a first capacitor that is connected to the first drain and to the second gate; and
a second capacitor that is connected to the second drain and to the first gate.
9. The circuit of claim 1 , wherein:
the resistor of the switchable RC network is a variable resistor that is implemented as either a PMOS (Positive-Channel Metal-Oxide Semiconductor) or an NMOS (Negative-Channel Metal-Oxide Semiconductor) transistor.
10. The circuit of claim 1 , wherein:
a value of the resistance of the switchable RC network is operative to control a boost between a low frequency gain and a high frequency gain of the circuit; and
a value of the capacitance of the switchable RC network is operative to control a peaking frequency of the circuit.
11. The circuit of claim 1 , wherein:
the first current source is a first current source transistor;
the second current source is a second current source transistor; and
the first differential transistor, the second differential transistor, the first current source transistor, and the second current source transistor are NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors.
12. A circuit, comprising:
a first differential transistor that includes a first source;
a second differential transistor that includes a second source;
a first current source that is connected to the first source;
a second current source that is connected to the second source; and
a switchable RC network, that includes a plurality of switches such that at least one of the plurality of switches, a resistor, and a capacitor are connected in parallel, that is operative to select an impedance from a plurality of impedances based on a connectivity of the plurality of switches, and that is connected between the first source and the second source; and wherein:
a value of the selected impedance of the switchable RC network is operative to control a boost between a low frequency gain and a high frequency gain of the circuit and is operative to control a peaking frequency of the circuit; and wherein:
the plurality of switches being operative either to short the first source to the second source or to select at least one of a resistance and a capacitance of the switchable RC network.
13. The circuit of claim 12 , wherein the switchable RC network comprising:
a plurality of capacitors; and
a plurality of resistors; and wherein:
the plurality of switches is operative to:
short the first source to the second source; or
select at least one of the plurality of capacitors and at least one of the plurality of resistors to be connected between the first source and the second source.
14. The circuit of claim 12 , wherein the switchable RC network comprising:
a variable resistor that is implemented as either a PMOS (Positive-Channel Metal-Oxide Semiconductor) or an NMOS (Negative-Channel Metal-Oxide Semiconductor) transistor.
15. The circuit of claim 12 , wherein:
the first differential transistor also includes a first gate and a first drain; and
the second differential transistor also includes a second gate and a second drain; and further comprising:
a first capacitor that is connected to the first drain and to the second gate; and
a second capacitor that is connected to the second drain and to the first gate.
16. The circuit of claim 12 , wherein:
the first current source is a first current source transistor;
the second current source is a second current source transistor; and
the first differential transistor, the second differential transistor, the first current source transistor, and the second current source transistor are NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors.
17. A circuit, comprising:
a first differential transistor that includes a first drain, first gate, and a first source;
a second differential transistor that includes a second drain, second gate, and a second source;
a first current source that is connected to the first source;
a second current source that is connected to the second source;
a switchable RC network, that includes a plurality of switches such that at least one of the plurality of switches, a resistor, and a capacitor are connected in parallel, that is operative to select an impedance from a plurality of impedances based on a connectivity of the plurality of switches, and that is connected between the first source and the second source;
a first input impedance that is connected to a first differential input of the circuit and to the first gate;
a second input impedance that is connected to a second differential input of circuit and to the second gate;
a first capacitor that is connected to the first drain and to the second gate; and
a second capacitor that is connected to the second drain and to the first gate; and wherein:
the plurality of switches being operative either to short the first source to the second source or to select at least one of a resistance and a capacitance of the switchable RC network.
18. The circuit of claim 17 , wherein the switchable RC network comprising:
a plurality of capacitors; and
a plurality of resistors; and wherein:
the plurality of switches is operative to:
short the first source to the second source; or
select at least one of the plurality of capacitors and at least one of the plurality of resistors to be connected between the first source and the second source.
19. The circuit of claim 17 , wherein:
the first differential transistor also includes a first drain; and
the second differential transistor also includes a second drain; and further comprising:
a first output impedance that is connected to the first drain and to a supply voltage; and
a second output impedance that is connected to the second drain and to the supply voltage.
20. The circuit of claim 17 , wherein:
the first current source is a first current source transistor;
the second current source is a second current source transistor; and
the first differential transistor, the second differential transistor, the first current source transistor, and the second current source transistor are NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors.