Pulse-Width Modulated Signal Generator for Light-Emitting Diode Dimming

1 . A circuit to control light-emitting-diode (LED) dimming of a display panel, comprising:

a first stage to receive a first PWM signal from an application driver, the first PWM signal having a first frequency and a first duty cycle;

a second stage to produce and transmit a second PWM signal, the second PWM signal having a second frequency according to the characteristics of the display panel and a second duty cycle according to the first duty cycle.

2 . A circuit as in claim 1 above, wherein the first stage further comprises a clock and logic gates to measure on-time and off-time intervals of said first PWM signal.

3 . A circuit as in claim 1 above, wherein the second PWM signal is provided a selected synchronization relative to the first PWM signal.

4 . A circuit as in claim 1 above, wherein the second frequency and the selected synchronization are chosen so as to provide synchronization with at least one of a horizontal and a vertical video refresh rate provided by the application driver.

5 . A circuit as in claim 1 above, wherein the second selected frequency is chosen such that a positive edge and a negative edge of said second PWM signal take place during blanking time.

6 . A backlight system for a Liquid Crystal Display (LCD) comprising:

an LCD panel comprising a two dimensional array of pixels;

an LED panel unit comprising a two-dimensional array with at least one LED unit per pixel;

a driving circuit for providing a PWM signal for LED dimming, the circuit further comprising:

a first stage to receive and measure the duty cycle of a first PWM signal, the first PWM signal operating at a first frequency;

a second stage to produce and transmit a second PWM signal with a second selected duty cycle, at a second selected frequency, and with a selected synchronization;

the first stage further comprising a clock to measure on-time and off-time intervals of the first PWM signal;

an LED controller circuit to receive a PWM signal from the driving circuit, and to provide a signal to the LED panel.

7 . A circuit for processing pulse-width-modulated (PWM) signals, comprising:

a first stage to receive and measure the duty cycle of a first PWM signal, the first PWM signal operating at a first frequency;

a second stage to produce and transmit a second PWM signal with a second selected duty cycle, at a second selected frequency and with a selected synchronization;

the first stage further comprising a clock and logic gates to measure on-time and off-time intervals of the first PWM signal.

8 . A circuit as in claim 7 above, further wherein

a synchronization signal is externally provided to the second stage of the circuit; and

the second stage produces the second PWM signal with a preselected phase-shift, relative to the synchronization signal externally provided.

9 . A method to control light-emitting-diode (LED) dimming by using pulse-width-modulated (PWM) signals, comprising:

receiving a first PWM signal having a first frequency;

measuring the duty cycle of the first PWM signal;

providing a second PWM signal at a second frequency with a second selected duty cycle.

10 . The method of claim 9 , wherein providing a second PWM signal further comprises:

providing a PWM signal with a selected synchronization;

using a clock to measure on-time and off-time intervals of the first PWM signal for the measuring of the duty cycle of a first PWM signal; and

transmitting the second PWM signal to an LED driver circuit.

11 . The method of claim 9 wherein using a clock to measure on-time and off-time intervals of the first PWM signal for the measuring of the duty cycle of a first PWM signal further comprises:

using an internal clock signal comprising a sequence of pulses occurring substantially faster than the first PWM signal, said first PWM signal having High portions and Low portions;

using a series of logic gates to compare the first PWM signal to the internal clock signal;

providing a first sequence of pulses corresponding to the internal clock pulses overlapping in time with the High portions of the first PWM signal;

providing a second sequence of pulses corresponding to the internal clock pulses overlapping in time with the Low portions of the first PWM signal;

counting the number of pulses in the first sequence of pulses and in the second sequence of pulses;

finding the duty cycle as the ratio between the number of pulses in the first sequence of pulses to the total number of pulses in the internal clock signal.