Semiconductor device and method of manufacturing the same
View Patent ↗A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers, a first gate pattern formed over a portion of the second conductivity-type well, a second gate pattern formed over one of the device isolation layers, a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern, a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern, and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from the second conductivity-type well.
1. An apparatus comprising:
a first conductivity-type deep well formed in a substrate;
a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed;
a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers;
a first gate pattern formed over a portion of the second conductivity-type well;
a second gate pattern formed over one of the device isolation layers;
a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern;
a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern; and
a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from the second conductivity-type well.
2. The apparatus of claim 1 , including:
a second conductivity-type doping region formed in an upper surface of the second conductivity-type well adjoining the source region.
3. The apparatus of claim 1 , wherein the device isolation layers include a first device isolation layer, a second device isolation layer, and a third device isolation layer.
4. The apparatus of claim 3 , wherein the second conductivity-type well is formed in a portion of the first conductivity-type deep well between the first and the second device isolation layers.
5. The apparatus of claim 3 , wherein the second conductivity-type well is formed in a part of the first conductivity-type deep well between the second and the third device isolation layers.
6. The apparatus of claim 5 , including a first conductivity-type well formed in the first conductivity-type deep well.
7. The apparatus of claim 6 , wherein the second drain region is formed in the first conductivity-type well.
8. The apparatus of claim 3 , wherein the first drain region is formed to include an interface between upper surfaces of the second conductivity-type well and the first conductivity-type deep well.
9. The apparatus of claim 3 , including:
a first spacer covering a first sidewall of the first gate pattern and a part of the first source region;
a second spacer covering the a second sidewall of the first gate pattern and a first part of the first drain region;
a third spacer covering a first sidewall of the second gate pattern and a second part of the first drain region; and
a fourth spacer covering the second sidewall of the second gate pattern and a part of the second device isolation layer.
10. The apparatus of claim 1 , including:
first conductivity-type lightly doped drain regions formed to overlap with a part of the first gate pattern adjoining the source region, and a part of the first gate pattern adjoining the first drain region.
11. The apparatus of claim 1 , wherein the source region, and the first and the second drain regions are of a first conductivity type.
12. A method comprising:
forming a first conductivity-type deep well by implanting first conductivity-type impurity ions into a substrate;
forming a second conductivity-type well in a part of the first conductivity-type deep well, by implanting second conductivity-type impurity ions into the substrate;
forming device isolation layers on the substrate in which the first conductivity-type deep well and the second conductivity-type well are formed;
forming a first gate pattern over a part of the second conductivity-type well and a second gate pattern over one of the device isolation layers;
forming a source region in an upper surface of the second conductivity-type well, adjoining a first side of the first gate pattern, by implanting first conductivity-type impurity ions into the substrate;
forming a first drain region to include the interface between an upper surface of the second conductivity-type well, which adjoins a second side of the first gate pattern, and an upper surface of the first conductivity-type deep well, by implanting first conductivity-type impurity ions into the substrate; and
forming a second drain region in an upper surface of the first conductivity-type deep well at an interval from the second conductivity-type well, by implanting first conductivity-type impurity ions into the substrate.
13. The method of claim 12 , wherein the source region, the first drain region and the second drain region are simultaneously formed using one mask.
14. The method of claim 12 , including:
forming a second conductivity-type doping region in an upper surface of the second conductivity-type well adjoining the source region, by implanting second conductivity-type impurity ions into the substrate.
15. The method of claim 12 , wherein the forming of the device isolation layers is performed by forming first, second and third device isolation layers in the substrate in which the first conductivity-type deep well and the second conductivity-type well are formed.
16. The method of claim 15 , wherein the second conductivity-type well is formed in a part of the first conductivity-type deep well between the first device isolation layer and the second device isolation layer.
17. The method of claim 12 , including:
forming a first conductivity-type well in a second part of the first conductivity-type deep well at an interval from the second conductivity-type well, by implanting first conductivity-type impurity ions into the substrate.
18. The method of claim 17 , wherein the second drain region is formed in the first conductivity-type well.
19. The method of claim 15 , wherein the first drain region is formed to include the interface between the upper surfaces of the second conductivity-type well and the first conductivity-type deep well, and to be disposed between the second side of the first gate pattern and the second device isolation layer.
20. The method of claim 15 , including:
forming a first spacer covering a first sidewall of the first gate pattern and a part of the first source region;
forming a second spacer covering a second sidewall of the first gate pattern and a first part of the first drain region;
forming a third spacer covering a first sidewall of the second gate pattern and a second part of the first drain region; and
forming a fourth spacer covering a second sidewall of the second gate pattern and a part of the second device isolation layer.