IP Library Granted Patent US 7,911,222
Granted Patent B2
US 7,911,222 · App. 12/571,740 · Granted Mar 22, 2011

Mix mode driver for traces of different lengths

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Quick Facts
Patent No.
US 7,911,222
App. No.
12/571,740
Granted
Mar 22, 2011
Kind
B2
Abstract

A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to generate a variable amplitude data output signal. Each stage is operable to increase or decrease a data signal, and each of the coefficient signals determines the magnitude of increase or decrease of the data input signal by a stage. A method for operating the mix mode driver includes generating the variable amplitude data output signal with one or more of the stages, and providing the variable amplitude data output signal to a trace.

Claims (37)

1. A method for programming a mix mode driver with a plurality of stages to accommodate traces of different lengths, the method comprising:

storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length, the one or more control signals selecting a number of the stages to generate a variable amplitude data output signal, each stage being operable to increase or decrease a data input signal, and each of the coefficient signals determining a magnitude of increase or decrease of the data input signal by a stage.

2. The method of claim 1 , wherein the variable amplitude data output signal has a greater or smaller signal swing than the data input signal, and each of the coefficient signals comprises a positive or a negative coefficient value.

3. The method of claim 1 , further comprising:

storing in the mix mode driver an other set of one or more control signals and coefficient signals for an other trace length;

determining a length of a trace; and

storing in the mix mode driver a select signal based on the length of the trace, the select signal selecting one of the set and the other set for the stages to generate the data output signal.

4. A method for operating a mix mode driver with a plurality of stages, comprising:

receiving one or more control signals selecting a number of the stages to generate a variable amplitude data output signal, each stage being operable to increase or decrease a data input signal;

receiving coefficient signals, each of the coefficient signals determining a magnitude of increase or decrease of the data input signal by a stage;

generating the variable amplitude data output signal with one or more of the stages; and

providing the variable amplitude data output signal to a trace.

5. The method of claim 4 , wherein the variable amplitude data output signal has a greater or smaller signal swing than the data input signal, and each of the coefficient signals comprises a positive or a negative coefficient value.

6. The method of claim 4 , further comprising sequentially providing the data input signal to the one or more of the stages.

7. The method of claim 6 , wherein generating the variable amplitude data output signal comprises coupling the one or more of the stages to an adder in response to the one or more control signals, the adder summing output signals from the one or more of the stages to generate the variable amplitude data output signal.

8. The method of claim 4 , wherein receiving the one or more control and the coefficient signals comprises using a multiplexer to selectively couple one of a plurality of registers to the stages, the registers storing sets of control and coefficient signals for different trace lengths.

9. A mix mode driver for driving a trace, comprising:

a plurality of stages being selectively combinable to increase and decrease a data input signal;

a timing circuit providing sequential outputs of the data input signal to the stages; and

an adder summing output signals from the stages to generate a variable amplitude data output signal;

wherein:

the stages comprises comprise:

a first stage comprising a first multiplier having an input terminal coupled to receive the data input signal, the first multiplier increasing or decreasing the data input signal by a first coefficient;

a second stage comprising:

a second multiplier having an input terminal coupled to receive the data input signal from a first data output terminal of the timing circuit, the second multiplier increasing or decreasing the data input signal by a second coefficient; and

a first switch having an input terminal coupled to an output terminal of the second multiplier;

a third stage comprising:

a third multiplier having an input terminal coupled to receive the data input signal from a second data output terminal of the timing circuit, the third multiplier increasing or decreasing the data input signal by a third coefficient; and

a second switch having an input terminal coupled to an output terminal of the third multiplier; and

input terminals of the adder are coupled to output terminals of the first multiplier, the first switch, and the second switch.

10. The mix mode driver of claim 9 , wherein the timing circuit comprises:

a first flip-flop having an input terminal coupled to receive the data input signal, the first flip-flop having an output terminal coupled to the input terminal of the second multiplier; and

a second flip-flop having an input terminal coupled to the output terminal of the first flip-flop, the second flip-flop having an output terminal coupled to the input terminal of the third multiplier.

11. The mix mode driver of claim 9 , further comprising:

one or more registers each storing a set of coefficient signals for the first, the second, and the third multipliers, and control signals for the first and the second switches; and

a multiplexer coupling control terminals of the first multiplier, the second multiplier, the third multiplier, the first switch, and the second switch to one of the registers to receive the coefficient and the control signals.

12. The mix mode driver of claim 9 , wherein the variable amplitude data output signal has a greater or smaller signal swing than the data input signal, and each coefficient signal comprises a positive or a negative coefficient value.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2011
From: 3PAR INC.
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 026250/0322 →