Nonvolatile semiconductor memory device
View Patent ↗In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.
1. A nonvolatile semiconductor memory device comprising:
a memory cell formed on a substrate of a first conductivity type, for storing information in a nonvolatile manner, said memory cell including an electric charge accumulation region formed on said substrate region and storing said information in an electric charge form, and a control electrode layer formed on said electric charge accumulation region and receiving a voltage for writing and reading storage information of said memory cell;
a bottom well of a second conductivity type region formed surrounding bottom and side portions of said substrate region;
a first voltage control circuit for setting a voltage of said substrate region; and
a second voltage control circuit operating individually and separately from voltage setting by said first voltage control circuit, for setting a voltage of said bottom well region according to an operation mode, to adjust the voltage level of said substrate region.