Processor-bus-connected flash storage nodes with caching to support concurrent DMA accesses from multiple processors

1. A system comprising a plurality of nodes coupled using a network of processor buses, wherein the plurality of nodes comprises:

a first processor node comprising one or more processing cores and main memory; and

a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses, the flash memory node comprising:

a flash memory comprising a plurality of flash pages;

a first memory comprising:

a cache partition for storing cached flash pages for the plurality of flash pages in the flash memory; and

a control partition for storing cache control data and contexts of requests to access the plurality of flash pages; and

a logic module comprising a direct memory access (DMA) register and configured to:

receive a first request from the first processor node via the first processor bus to access the plurality of flash pages, wherein the first request is received using the DMA register that is mapped into an address space of the first processor node,

store one or more parameters of the first request as a first context of the contexts stored in the control partition of the first memory,

schedule a DMA operation responsive to the first request, and

perform the DMA operation based on the first context,

wherein the DMA operation transfers data between the flash memory and the first processor node and comprises accessing the cache partition in the first memory when a portion of the plurality of flash pages is cached in the cache partition according to the cache control data.

2. The system of claim 1 ,

wherein performing the DMA operation further comprises issuing a command of the processor bus to transfer data between the flash memory and the first processor node,

wherein the logic module is further configured to generate an interrupt to the processor when the DMA operation is completed, and

wherein the flash memory node further comprises a second memory for storing cached portions of the control partition of the first memory.

3. The system of claim 1 ,

wherein the control partition of the first memory further comprises a flash page address mapping table,

wherein the logic module is further configured to generate, based on the flash page address mapping table, a cached flash page address in the cache partition from a flash page address comprised in the one or more parameters, and

wherein the DMA operation is performed based at least on the cached flash page address.

4. The system of claim 1 ,

wherein the flash memory is a virtual memory paging device for the first processor node,

wherein the control partition of the first memory further comprises a virtual address mapping table,

wherein the logic module is further configured to generate, based on the virtual address mapping table, at least one of a flash page address in the flash memory and a cached flash page address in the cache partition from a virtual address comprised in the one or more parameters, and

wherein the DMA operation is based on the at least one of the flash page address in the flash memory and the cached flash page address in the cache partition.

5. The system of claim 2 ,

wherein the first request is generated by a first thread executing on a first processor core of the one or more processor cores in the first processor node,

wherein the logic module is further configured to:

receive a second request via a second processor bus to access the plurality of flash pages, wherein the second request is generated by a second thread running on one of a group consisting of the first processor core and a second processor core, wherein the second processor core is located in one of a group consisting of the first processor node and a second processor node of the plurality of processor nodes, the second processor node coupled to the flash memory node via the second processor bus of the processor buses;

store the second request as a second context of the contexts stored in the control partition of the first memory;

schedule a second DMA operation responsive to the second request; and

perform the second DMA request based on the second context concurrently with the first DMA operation.