Semiconductor device and method for manufacturing the same
View Patent ↗Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes at least two of first and second conductive-type high-voltage transistors and first and second conductive-type low-voltage transistors. The first conductive-type high-voltage transistor include a first conductive-type well in a semiconductor substrate, a device isolation film in the first conductive-type well, a gate pattern on the first conductive-type well, second conductive-type drift regions in the semiconductor substrate at opposite sides of the gate pattern, second conductive-type source and drain regions in the second conductive-type drift region, a pick-up region to receive a bias voltage, and a first latch-up inhibiting region under the pick-up region. Accordingly, it is possible to reduce and prevent latchup without using a double guard ring and to eliminate an additional process to form first and second latch-up inhibiting regions.
1. A semiconductor device in an integrated circuit comprising at least two of first and second conductive-type high-voltage transistors and first and second conductive-type low-voltage transistors, wherein the first conductive-type high-voltage transistor comprises:
a first conductive-type well in a semiconductor substrate;
a device isolation film in the first conductive-type well;
a gate pattern on the first conductive-type well;
second conductive-type drift regions in the semiconductor substrate at opposite sides of the gate pattern;
second conductive-type source and drain regions in the second conductive-type drift regions;
a pick-up region configured to receive a bias voltage; and
a first latch-up inhibiting region under the pick-up region.
2. The semiconductor device according to claim 1 , further comprising a second latch-up inhibiting region under the first latch-up inhibiting region.
3. The semiconductor device according to claim 2 , wherein the first and second latch-up inhibiting regions have the first conductive type.
4. The semiconductor device according to claim 1 , wherein the first latch-up inhibiting region has the first conductive type.
5. The semiconductor device according to claim 1 , wherein a concentration of the first latch-up inhibiting region is equivalent to a concentration of the second conductive-type drift region of the second conductive-type high-voltage transistor.
6. The semiconductor device according to claim 5 , wherein a concentration of the second latch-up inhibiting region is equivalent to a concentration of the second conductive-type well of the first conductive-type low-voltage transistor.
7. The semiconductor device according to claim 6 , wherein a concentration of the second latch-up inhibiting region is higher than a concentration of the well.
8. The semiconductor device according to claim 1 , wherein a concentration of the first latch-up inhibiting region is equivalent to a concentration of the second conductive-type well of the first conductive-type low-voltage transistor.
9. The semiconductor device according to claim 8 , wherein a concentration of the first latch-up inhibiting region is higher than a concentration of the second latch-up inhibiting region.
10. The semiconductor device according to claim 1 , wherein a concentration of the first latch-up inhibiting region is higher than a concentration of the well.
11. The semiconductor device according to claim 1 , comprising the first conductive-type high-voltage transistor and the second conductive-type high-voltage transistor.