Connection for off-chip electrostatic discharge protection
View Patent ↗A method and apparatus for off-chip ESD protection, the apparatus includes an unprotected IC 22 stacked on an ESD protection chip 24 and employing combinations of edge wrap 32 and through-silicon via connectors 44 for electrical connection from an external connection lead 34 on a chip carrier 84 or system substrate 64 , to an ESD protection circuit, and to an I/O trace 46 of the unprotected IC 22 . In one embodiment the invention provides an ESD-protected stack 50 of unprotected IC chips 52, 54 that has reduced hazard of mechanical and ESD-damage in subsequent handling for assembly and packaging. The method includes a manufacturing method 170 for mass producing embedded edge wrap connectors 32, 38 during the chip manufacturing process.
1. A semiconductor stack assembly having ESD protection comprising, a first chip including an integrated circuit (IC) with an input/output (I/O) trace without on-chip electrostatic discharge (ESD) protection; and
a second chip having an ESD protection circuit, said first chip being electrically connected to said second chip with a conductor to said ESD protection circuit and said I/O trace wherein said conductor is formed during manufacture of said chips; and
a substrate, on the second chip, including an external connection lead, wherein said second chip includes a contact surface comprising a back contact surface, disposed facing and matching a contact area of the external connection lead and electrically connected thereto by conductive material.
2. A semiconductor stack assembly having ESD protection as in claim 1 , wherein said conductor is selected from the group of connectors consisting of embedded edge wrap connector, edge wrap connector, and through-silicon via (TSV) connector.
3. A semiconductor stack assembly having ESD protection as in claim 1 , wherein no wire bonds are present.
4. A semiconductor stack assembly having ESD protection as in claim 1 , wherein the conductive material is one of the group of materials consisting of solder, metal, conductive polymer, conductive epoxy.
5. A semiconductor stack assembly having ESD protection as in claim 2 , wherein at least one of the first and second chips an upper surface portion adapted for wire bonding, and wherein a contact surface for external connection comprises a wire bonding pad disposed on the upper surface portion.
6. A semiconductor stack assembly having ESD protection as in claim 5 , wherein the upper surface portion is on a chip protruding from the stack.
7. A semiconductor stack assembly having ESD protection comprising, a first chip including an integrated circuit (IC) with an input/output (I/O) trace without on-chip electrostatic discharge (ESD) protection; and
a second chip having an ESD protection circuit, said first chip being electrically connected to said second chip with a conductor to said ESD protection circuit and said I/O trace wherein said conductor is formed during manufacture of said chips, wherein said conductor comprises an embedded edge wrap conductor substantially having a shape of a section of a cylinder.
8. A semiconductor stack assembly having ESD protection as in claim 7 , further comprising an enlarged area for attachment to an external attachment lead on a substrate.
9. A semiconductor stack assembly having ESD protection as in claim 7 , further comprising an enlarged area for attachment to an external attachment on a semiconductor chip.
10. A semiconductor stack assembly having ESD protection comprising, a first chip including an integrated circuit (IC) with an input/output (I/O) trace without on-chip electrostatic discharge (ESD) protection; and
a second chip having an ESD protection circuit, said first chip being electrically connected to said second chip with a conductor to said ESD protection circuit and said I/O trace wherein said conductor is formed during manufacture of said chips, wherein said conductor comprises an embedded edge wrap conductor substantially having a shape of a section of a frustoconical cone said section being on a plane parallel to the axis of the frustoconical cone.
11. A method for making an embedded edge wrap conductor from a blank of material for use for production of multiple IC chips upon separation comprising:
masking a masked area of the chip to create cove portions adjacent the area where the chips will be separated;
trenching the masked area to form a trench having sidewalls with coves in the masked areas;
insulating said sidewalls and coves in said trench;
removing insulation to open contact on said coves where contact is desired;
depositing conducting material in said trench and coves; and,
singulating the chips along said trench.
12. A method for making an embedded edge wrap conductor from a blank of material for use for production of multiple IC chips upon separation as in claim 11 , further comprising:
patterning the deposited conducting material to form conductors.
13. A method for making an embedded edge wrap conductor from a blank of material for use for production of multiple IC chips upon separation as in claim 12 , wherein said patterning is adapted to form the conductors to protrude from the sidewall.