Granted Patent B2

US 8,044,690 · App. 12/574,663 · Granted Oct 25, 2011

Abstract

Claims (87)

1. In a pulse modulator, a calibrated synchronized triangular waveform generator comprising:

a triangular waveform generator including a clock input for receiving a clock signal and a calibration code input for receiving a calibration code signal, the triangular waveform generator operable to output a triangular waveform in response to the received clock signal and calibration code signal;

a digital pulse generator configured to receive the triangular waveform and produce an internally generated clock signal sharing essentially a common frequency with the triangular waveform;

a calibration circuit operable to adjust the calibration code signal by comparing a frequency of an external clock signal and the frequency of the internally generated clock signal during calibration; and

clock selection circuitry selectively providing either the internally generated clock signal or the external clock signal to the clock input, wherein the internally generated clock signal is selected during calibration.

2. The pulse modulator of claim 1 wherein the clock selection circuitry comprises a multiplexer.

3. The calibrated synchronized triangle waveform generator of claim 1 wherein the digital pulse generator comprises:

a latch operable to generate the internally generated clock signal, wherein the latch is set to a low state when a predetermined high bias voltage is lower than the triangular waveform voltage and set to a high state when a predetermined low bias voltage is higher than the triangular waveform voltage.

4. The calibrated synchronized triangle waveform generator of claim 3 wherein the digital pulse generator further comprises:

a first comparator operable to compare the triangular waveform voltage with the high bias voltage and output a result to the latch; and

a second comparator operable to compare the triangular waveform voltage with the low bias voltage and output a result to the latch.

5. The calibrated synchronized triangular waveform generator of claim 1 , wherein the calibration circuit and the digital pulse generator arc deactivated when the calibrated synchronized triangular waveform generator is not in calibration.

6. The calibrated synchronized triangular waveform generator of claim 1 , wherein the calibration circuit comprises:

a rate comparison circuit operable to compare a first number of cycles of the external clock signal and a second number of cycles of the internally generated clock signal;

a successive approximation register operable to adjust the calibration code on the basis of whether the first number is greater than the second number.

7. The calibrated synchronized triangular waveform generator of claim 6 , wherein the rate comparison circuit comprises:

a first counter operable to count the first number;

a second counter operable to count the second number, wherein the second counter stops counting when the first counter counts a predetermined number of cycles.

8. The calibrated synchronized triangular waveform generator of claim 1 , the triangular waveform generator comprises:

a rising sawtooth waveform generator operable to produce a rising sawtooth waveform;

a falling sawtooth waveform generator operable to produce a falling sawtooth waveform; and

complementary switching circuits operable to alternatively output one of the rising sawtooth waveform and the falling sawtooth waveform to generate the triangular waveform.

9. The pulse modulator of claim 8 wherein each sawtooth waveform generator further comprises:

a capacitor; and

an adjustable current source for charging the capacitor, wherein the output of the adjustable current source is controlled by the calibration code.

10. A method of generating a triangular waveform synchronized to an external clock signal comprising:

generating a triangular waveform having a voltage on the basis of a calibration code signal and a clock signal;

during calibration, selecting an internally generated clock signal as the clock signal;

during calibration, generating the internally generated clock signal wherein the internally generated clock signal and the generated triangular waveform essentially share a common frequency;

during calibration, adjusting the calibration code signal on the basis of the external clock signal and the internally generated clock signal; and

after calibration, freezing the calibration code signal;

wherein adjusting the calibration code signal comprises:

comparing a first number of cycles of the external clock signal with a second number of cycles of the internally clock signal; and

refining an approximation to a calibration code on the basis of whether the first number is greater than the second number.

11. The method of claim 10 , wherein generating the internally generated clock signal comprises:

comparing the voltage of the triangular waveform with a high bias voltage and forcing the internally generated clock signal into a low state when the voltage is greater than or equal to the high b as voltage; and

comparing the voltage of the triangular waveform with a low bias voltage and forcing the internally generated clock signal into a high state when the voltage is less than or equal to the low bias voltage.

12. The method of claim 11 , wherein the calibration code comprises b bits and refining the approximation comprises:

setting n to b; and

repeating while n is greater than 1, an iteration comprising:

setting the nth bit in the calibration code; and

if the second number is greater than the first number then clearing the nth bit in the calibration code.

13. The method of claim 11 , wherein the comparing comprises:

counting, the first number of cycles;

counting the second number of cycles until the first number of cycles reaches a predetermined number of cycles.

14. The method of claim 10 wherein generating a triangular waveform comprises:

when the clock signal is in the high state generating a rising sawtooth waveform having a voltage with a slope controlled by the calibration code signal; and

when the clock signal is in the low state generating a falling sawtooth waveform having a voltage with a slope controlled by the calibration code signal.

15. A calibrated triangular waveform generator synchronized to an external clock signal comprising:

means for generating a triangular waveform having a voltage on the basis of a calibration code signal and a clock signal;

means for selecting an internally generated clock signal as the clock signal;

means for generating the internally generated clock signal comprising:

means for comparing the voltage of the triangular waveform with a high bias voltage and forcing the internally generated clock signal into a low state when the voltage is greater than or equal to the high bias voltage; and

means for comparing the voltage of the triangular waveform with a low bias voltage and forcing the internally generated clock signal into a high state when the voltage is less than or equal to the low bias voltage;

means for adjusting the calibration code signal on the basis of the external clock signal and the internally generated clock signal, the means for adjusting further comprising:

means for comparing a first number of cycles of the external clock signal with a second number of cycles of the internally clock signal; and

means for refining an approximation to a calibration code on the basis of whether the first number is greater than the second number; and

means for freezing the calibration code signal.

16. The calibrated triangular waveform generator of claim 15 , further comprising means for deactivating the means for generating the internally generated clock signal and the means for adjusting the calibration code signal after calibration.

17. The calibrated triangular waveform generator of claim 15 wherein generating a triangular waveform comprises:

means for generating a rising sawtooth waveform having a voltage with a slope controlled by the calibration code signal;

means for generating a falling sawtooth waveform having a voltage with a slope controlled by the calibration code signal; and

switching means for selecting the means for generating a rising sawtooth waveform and the means for generating a falling sawtooth on the basis of the clock signal.

18. A waveform generator comprising:

a triangular waveform generator including a clock input for receiving a clock signal and a calibration code input for receiving a calibration code signal, the triangular waveform generator operable to output a triangular waveform in response to the received clock signal and calibration code signal;

a digital pulse generator configured to receive the triangular waveform and produce an internally generated clock signal sharing essentially a common frequency with the triangular waveform; and

a calibration circuit operable to adjust the calibration code signal by comparing a frequency of an external clock signal and the frequency of the internally generated clock signal during calibration, the calibration circuit comprising:

a rate comparison circuit operable to compare a first number of cycles of the external clock signal and a second number of cycles of the internally clock signal;

a successive approximation register operable to adjust the calibration code on the basis of whether the first number is greater than the second number.

19. The waveform generator of claim 18 further comprising clock selection circuitry selectively providing either the internally generated clock signal or the external clock signal to the clock input, wherein the internally generated clock signal is selected during calibration.

20. The waveform generator of claim 18 wherein the digital pulse generator comprises a latch operable to generate the internally generated clock signal, wherein the latch is set to a low state when a predetermined high bias voltage is lower than the triangular waveform voltage and set to a high state when a predetermined low bias voltage is higher than the triangular waveform voltage.

21. The waveform generator of claim 20 wherein the digital pulse generator further comprises:

a first comparator operable to compare the triangular waveform voltage with the high bias voltage and output the result to the latch; and

a second comparator operable to compare the triangular waveform voltage with the low bias voltage and output the result to the latch.

22. The waveform generator of claim 18 , wherein the rate comparison circuit comprises:

a first counter operable to count the first number;

a second counter operable to count the second number, wherein the second counter stops counting when the first counter counts a predetermined number of cycles.

23. A waveform generator comprising:

a triangular waveform generator including a clock input for receiving a clock signal and a calibration code input for receiving a calibration code signal, the triangular waveform generator operable to output a triangular waveform in response to the received clock signal and calibration code signal, the triangular waveform generator further comprising:

a rising sawtooth waveform generator operable to produce a rising sawtooth waveform;

a falling sawtooth waveform generator operable to produce a falling sawtooth waveform; and

complementary switching circuits operable to alternatively output one of the rising sawtooth waveform and the falling sawtooth waveform to generate the triangular waveform; and

wherein each sawtooth waveform generator further comprises:

a capacitor: and

an adjustable current source for charging the capacitor. wherein the out-put of the adjustable current source is controlled by the calibration code;

a digital pulse generator configured to receive the triangular waveform and produce an internally generating clock signal sharing essentially a common frequency with the triangular waveform; and

a calibration circuit operable to adjust the calibration code signal by comparing the frequency of an external clock signal and the frequency of the internally generated clock signal during calibration.

Assignments (11)