IP Library Granted Patent US 7,956,688
Granted Patent B2
US 7,956,688 · App. 12/574,923 · Granted Jun 7, 2011

Common mode cancellation in differential networks

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Quick Facts
Patent No.
US 7,956,688
App. No.
12/574,923
Granted
Jun 7, 2011
Kind
B2
Abstract

Embodiments of the invention include a common mode cancellation circuit and method for correcting signal skew in a differential circuit. According to one embodiment, an op amp circuit is used to correct the mismatch between transmission line lengths in the differential circuit. The CMCC can be embodied as an ASIC and added on to an existing differential signaling systems to correct and compensate for board wiring skew or other causes of phase misalignment. The result is restoration of the cross-over intersection of the plus and minus signals of the differential pair closer to the common voltage level point, as if the signals had been in phase.

Claims (25)

1. A differential signaling system, comprising:

a pair of differential transmission lines of unequal length and having a common mode node between the differential transmission lines;

an operational amplifier having a negative input coupled to the common mode node and a positive input coupled to a resistor divider that sets the DC voltage at the positive input equal to a voltage of the common mode node;

a pair of transistors coupled to the output of the operational amplifier, with emitters of the transistors coupled only to the longer of the pair of differential transmission lines, wherein only one of the transistors is reverse-biased;

a first resistor in series between the common mode node and the first differential negative input; and

a second resistor in parallel with the operational amplifier, wherein the ratio of second resistor to the first resistor is less than an open-loop gain of the operational amplifier.

2. The differential signaling system of claim 1 , wherein the differential transmission lines are included on a circuit board, and wherein the operational amplifier, the resistor divider, and the transistors are included in an application-specific integrated circuit externally coupled to the circuit board.

3. The differential signaling system of claim 1 , wherein the differential transmission lines are included on a circuit board, the system further comprising:

a first electronic component including a driver coupled to the circuit board for generating a differential signal on the differential transmission lines; and

a second electronic component including a receiver coupled to the circuit board for receiving the differential signal.

4. The differential signaling system of claim 3 , wherein the circuit board comprises a midplane or backplane of a multi-server chassis.

5. The differential signaling system of claim 4 , wherein one or both of the first and second electronic components comprises a blade server.

6. A method, comprising:

transmitting a differential signal over complementary signal paths of unequal length between a driver and a receiver; and

resisting a change in crossover voltage of the differential signal at a common mode node between the complementary signal paths near the receiver by automatically injecting electrical current only into the longer of the complementary signal paths;

detecting a common mode voltage change from a steady state level; and

adjusting the gain of an operational amplifier and the magnitude of a resistor divider at a differential input to the operational amplifier to establish op-amp input levels.

7. The method of claim 6 , further comprising:

performing a pull up action on the differential signal component transmitted on the longer signal path during a rising voltage transition.

8. The method of claim 6 , further comprising:

increasing voltage or current at the common mode node in response to a rising voltage transition on the longer signal path.

9. The method of claim 6 , further comprising:

performing a pull down action on the differential signal component transmitted on the longer signal path during a falling voltage transition.

10. The method of claim 6 , further comprising:

decreasing voltage or current at the common mode node in response to a falling voltage transition on the longer signal path.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: LENOVO INTERNATIONAL LIMITED
Reel/Frame 034194/0291 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2009
From: AHMED, RUBINA F.; HERRMAN, BRADLEY D.; PATEL, PRAVIN; SEIDEL, PETER R.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023338/0779 →