Chip blanking and processing in SCDMA to mitigate impulse and burst noise and/or distortion
View Patent ↗A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication.
1. An apparatus, comprising:
an input that receives a first RS (Reed-Solomon) encoded signal;
a decoder that performs partial decoding of the first RS encoded signal thereby generating an error estimate corresponding to the first RS encoded signal; and wherein:
based on the error estimate, the decoder marks at least one symbol of the first RS encoded signal as an erasure thereby generating a second RS encoded signal; and
the decoder performs decoding of the second RS encoded signal thereby generating an estimate of at least one information bit encoded within the second RS encoded signal.
2. The apparatus of claim 1 , wherein:
the first RS encoded signal is an interleaved RS encoded signal.
3. The apparatus of claim 1 , further comprising:
a fidelity processor; and
a slicer that processes the first RS encoded signal thereby generating a plurality of hard decisions; and wherein:
during a first time, the slicer slices a first portion of the first RS encoded signal thereby generating a first hard decision of the plurality of hard decisions;
a first error power estimate is made based on a comparison of the first hard decision and the first portion of the first RS encoded signal;
during a second time, the slicer slices a second portion of the first RS encoded signal thereby generating a second hard decision of the plurality of hard decisions;
a second error power estimate is made based on a comparison of the second hard decision and the second portion of the first RS encoded signal;
the fidelity processor generates a channel fidelity metric based on at least one of the first error power estimate and the second error power estimate; and
based on both the error estimate and the channel fidelity metric, the decoder marks the at least one symbol of the first RS encoded signal as an erasure thereby generating the second RS encoded signal.
4. The apparatus of claim 1 , wherein:
the first RS encoded signal is an interleaved RS encoded signal that has been received from a communication channel that adds burst noise to the first RS encoded signal;
the burst noise affects a plurality of consecutive symbols within the first RS encoded signal; and
based on an interleaving pattern employed to generate the first RS encoded signal, upon de-interleaving the first RS encoded signal prior to the decoder performing partial decoding of the first RS encoded signal, burst noise affected symbols within the first RS encoded signal are dispersed within the de-interleaved, first RS encoded signal.
5. The apparatus of claim 1 , wherein:
the first RS encoded signal is an interleaved RS encoded signal that has been received from a communication channel that adds burst noise to the first RS encoded signal;
the burst noise affects a plurality of consecutive symbols within the first RS encoded signal;
each codeword of a codeword subset of a plurality of RS codewords, generated from the first RS encoded signal, includes at least one burst noise affected symbol based on an interleaving pattern employed to generate the first RS encoded signal; and
based on locations of the first burst noise affected symbol and the second burst noise affected symbol within the first codeword and the second codeword, respectively, the decoder marks at least one additional symbol of the first RS encoded signal as an erasure when generating the second RS encoded signal.
6. The apparatus of claim 5 , wherein:
the at least one additional symbol of the first RS encoded signal is the at least one symbol of the first RS encoded signal.
7. The apparatus of claim 1 , wherein:
the apparatus is a transceiver that also includes a transmitter.
8. An apparatus, comprising:
an input that receives a first forward error correction (FEC) encoded signal;
a decoder that performs partial decoding of the first FEC encoded signal thereby generating an error estimate corresponding to the first FEC encoded signal; and wherein:
based on the error estimate, the decoder marks at least one portion of the first FEC encoded signal as an erasure thereby generating a second FEC encoded signal; and
the decoder performs decoding of the second FEC encoded signal thereby generating an estimate of at least one information bit encoded within the second FEC encoded signal.
9. The apparatus of claim 8 , wherein:
the at least one portion of the first FEC encoded signal is a symbol of the first FEC encoded signal.
10. The apparatus of claim 8 , wherein:
the at least one portion of the first FEC encoded signal is a bit of the first FEC encoded signal.
11. The apparatus of claim 8 , wherein:
the first FEC encoded signal is a RS (Reed-Solomon) encoded signal.
12. The apparatus of claim 8 , wherein:
the first FEC encoded signal is an interleaved RS (Reed-Solomon) encoded signal.
13. The apparatus of claim 8 , further comprising:
a fidelity processor; and
a slicer that processes the first FEC encoded signal thereby generating a plurality of hard decisions; and wherein:
during a first time, the slicer slices a first portion of the first FEC encoded signal thereby generating a first hard decision of the plurality of hard decisions;
a first error power estimate is made based on a comparison of the first hard decision and the first portion of the first FEC encoded signal;
during a second time, the slicer slices a second portion of the first FEC encoded signal thereby generating a second hard decision of the plurality of hard decisions;
a second error power estimate is made based on a comparison of the second hard decision and the second portion of the first FEC encoded signal;
the fidelity processor generates a channel fidelity metric based on at least one of the first error power estimate and the second error power estimate; and
based on both the error estimate and the channel fidelity metric, the decoder marks the at least one symbol of the first FEC encoded signal as an erasure thereby generating the second FEC encoded signal.
14. The apparatus of claim 8 , wherein:
the first FEC encoded signal is an interleaved RS (Reed-Solomon) encoded signal that has been received from a communication channel that adds burst noise to the first FEC encoded signal;
the burst noise affects a plurality of consecutive symbols within the first FEC encoded signal; and
based on an interleaving pattern employed to generate the first FEC encoded signal, upon de-interleaving the first FEC encoded signal prior to the decoder performing partial decoding of the first FEC encoded signal, burst noise affected symbols within the first FEC encoded signal are dispersed within the de-interleaved, first FEC encoded signal.
15. The apparatus of claim 8 , wherein:
the first FEC encoded signal is an interleaved RS (Reed-Solomon) encoded signal that has been received from a communication channel that adds burst noise to the first FEC encoded signal;
the burst noise affects a plurality of consecutive symbols within the first FEC encoded signal;
each codeword of a codeword subset of a plurality of RS codewords, generated from the first FEC encoded signal, includes at least one burst noise affected symbol based on an interleaving pattern employed to generate the first FEC encoded signal; and
based on locations of the first burst noise affected symbol and the second burst noise affected symbol within the first codeword and the second codeword, respectively, the decoder marks at least one additional symbol of the first FEC encoded signal as an erasure thereby generating the second FEC encoded signal.
16. The apparatus of claim 15 , wherein:
the at least one additional symbol of the first FEC encoded signal is the at least one symbol of the first FEC encoded signal.
17. The apparatus of claim 8 , wherein:
the apparatus is a transceiver that also includes a transmitter.