Multi-functional integrated circuit and source driver having the same
View Patent ↗Disclosed are a multi-functional integrated circuit and a source driver having the same. The integrated circuit (IC) chip includes: a first high-voltage transistor configured to precharge a storage node in response to a first control signal; a decoding unit configured to decode a plurality of input signals to output the decoded signal to the storage node; and a second high-voltage transistor configured to transfer an output of the decoding unit to the storage node in response to a second control signal.
1. An integrated circuit (IC) chip, comprising:
a first high-voltage transistor configured to precharge a storage node in response to a first control signal;
a capacitor coupled to the storage node;
a decoding unit configured to decode a plurality of input signals and to output the decoded signal to the storage node; and
a second high-voltage transistor configured to transfer an output of the decoding unit to the storage node in response to a second control signal, wherein
the decoding unit includes a plurality of low-voltage transistors coupled between a first supply voltage terminal and the second high-voltage transistor in series.
2. The IC chip of claim 1 , wherein the capacitor includes a parasitic capacitor.
3. The IC chip of claim 1 , further comprising a buffer configured to output a signal at the storage node to outside.
4. The IC chip of claim 3 , wherein the buffer includes high-voltage transistors.
5. The IC chip of claim 1 , wherein the low-voltage transistors includes NMOS transistors whose gates receive the input signals.
6. The IC chip of claim 1 , wherein the first high-voltage transistor includes a high-voltage PMOS transistor having a source-drain path connected between a second supply voltage terminal and the storage node, and a gate receiving the first control signal.
7. The IC chip of claim 1 , wherein the second high-voltage transistor includes a high-voltage NMOS transistor having a source-drain path connected between the storage node and an output node of the decoding unit, and a gate receiving the second control signal.
8. The IC chip of claim 1 , wherein the decoding unit and first and second high-voltage transistors cooperate to shift low-voltage levels of the input signals to high-voltage levels stored by the storage node.
9. The IC chip of claim 1 , wherein one end of the capacitor is connected to the storage node and another end of the capacitor is connected to ground.
10. A source driving device, comprising:
a sampling latch configured to sample and latch image data input from outside;
a circuit block configured to pre-decode data output from the sampling latch, and shift and store a voltage level of the pre-decoded data in response to a control signal; and
a decoder configured to decode the pre-decoded image data and to transfer one of a plurality of gradation voltages, wherein:
the circuit block includes:
a first high-voltage transistor configured to precharge a storage node in response to a first control signal;
a capacitor coupled to the storage node;
a pre-decoding unit configured to decode a plurality of input signals and to output the decoded signal to the storage node; and
a second high-voltage transistor configured to transfer an output of the decoding unit to the storage node in response to a second control signal, and
the pre-decoding unit includes a plurality of low-voltage transistors coupled between a first supply voltage terminal and the second high-voltage transistor in series.
11. The source driving device of claim 10 , wherein the capacitor includes a parasitic capacitor.
12. The source driving device of claim 10 , further comprising a buffer configured to output a signal at the storage node to outside.
13. The source driving device of claim 12 , wherein the buffer includes high-voltage transistors.
14. The source driving device of claim 10 , wherein the low-voltage transistors include NMOS transistors whose gates receive the input signals.
15. The source driving device of claim 10 , further comprising a test unit configured to make some output signals of plural circuits in the pre-decoding unit corresponding to the circuit block to have the same logic value for a reliability test of the pre-decoding unit.
16. The source driving device of claim 15 , wherein the test unit includes a plurality of low-voltage transistors.
17. The source driving device of claim 10 , wherein the first high-voltage transistor includes a high-voltage PMOS transistor having a source-drain path connected between a second supply voltage terminal and the storage node, and a gate receiving the first control signal.
18. The source driving device of claim 10 , wherein the second high-voltage transistor includes a high-voltage NMOS transistor having a source-drain path connected between the storage node and an output node of the decoding unit, and a gate receiving the second control signal.
19. The source driving circuit of claim 10 , wherein the pre-decoding unit and first and second high-voltage transistors cooperate to shift low-voltage levels of the input signals to high-voltage levels stored by the storage node.
20. An integrated circuit (IC) chip, comprising:
a first high-voltage transistor configured to precharge a storage node in response to a first control signal;
a capacitor coupled to the storage node;
a decoding unit configured to decode input signals and to output a decoded signal to the storage node; and
a second high-voltage transistor configured to transfer an output of the decoding unit to the storage node in response to a second control signal, wherein
the decoding unit and the first and second high-voltage transistors cooperate to shift low-voltage levels of the input signals to high-voltage levels stored by the storage node.