Transistor with raised source and drain formed on SOI substrate
View Patent ↗Embodiments relate to a method for fabricating a transistor by using a SOI wafer. A gate insulation layer and a first gate conductive layer on a silicon-on-insulator substrate of a substrate to form a first gate conductive pattern, a gate insulation layer pattern, and a silicon layer pattern. A device isolation insulation layer exposing the top surface of the first gate conductive layer pattern may be formed. A second gate conductive layer may be formed. A mask pattern may be formed. Then, a gate may be formed by etching. After forming a source and drain conductive layer on the silicon layer pattern, the mask pattern may be removed. A salicide layer may be selectively contacting the gate and the source and drain conductive layer may be formed.
1. A transistor with raised source and drain formed on SOI substrate comprising:
an SOl substrate including a substrate layer, a middle insulation layer, and a silicon layer pattern;
device isolation insulation layers over and contacting the middle insulation layer, and beside and contacting the silicon layer pattern;
a gate insulation layer formed over a portion of the silicon layer pattern;
a gate insulation layer pattern formed beside the device isolation insulation layers and apart from the gate insulation layer and having the same height and material with the gate insulation layer;
a gate electrode including a first gate conductive layer pattern formed over a portion of the gate insulation layer and a second gate conductive layer pattern formed over the first gate conductive layer pattern;
a first gate conductive layer spacers formed on and contacting the gate insulation layer pattern and a sidewall of the device isolation insulation layers and having same material with the first gate conductive layer pattern;
a insulation layer spacers formed adjacent to sides of the gate electrode and over a portion of the gate insulation layer;
source and drain conductive layer formed over the silicon layer pattern and beside the gate insulation layer, the gate insulation layer pattern, the first gate conductive layer spacers and a portion of the insulation layer spacers; and
a salicide layer formed over each of the gate electrode and the source and drain conductive layer.
2. The transistor of claim 1 , wherein the first gate conductive layer pattern and the second gate conductive layer pattern each comprise a polysilicon layer.
3. The transistor of claim 1 , wherein the first gate conductive layer spacers comprise a polysilicon layer.
4. The transistor of claim 1 , wherein the salicide layer is formed over a top surface of the first gate conductive layer spacers, source and drain conductive layer.
5. The transistor of claim 1 , wherein the salicide layer comprises at least one of Ti-based salicide, Co-based salicide, Ta-based salicide, and Ni-based salicide.
6. A device comprising:
an SOl substrate, including a substrate layer, a middle insulation layer, and a silicon layer;
device isolation insulation layers over and contacting the middle insulation layer;
a gate insulating layer formed over a portion of the SOI substrate;
a gate electrode formed over a first portion of the gate insulating layer;
a first gate conductive layer spacers on and contacting a second portion of the gate insulating layer and a sidewall of the device isolation insulation layers;
insulating sidewalls formed adjacent to sides of the gate electrode and over the gate insulating layer;
source and drain regions formed over the SOI substrate and between and contacting the first gate conductive layer spacers and over and contacting the silicon layer; and
a salicide layer formed over each of the gate electrode and the source and drain regions,
wherein the insulating sidewalls is spaced apart from the respective first gate conductive layer spacers and are formed on and contacting sidewalls of the gate electrode.
7. The device of claim 6 , wherein the gate electrode comprises a first gate conductive layer formed over the gate insulator layer and a second gate conductive layer formed over the first gate conductive layer.
8. The device of claim 7 , wherein the device isolation insulation layers are spaced apart from the first and the second gate conductive layer.
9. The device of claim 7 , wherein the first gate conductive layer and the second gate conductive layer each comprise a polysilicon layer.
10. The device of claim 6 , wherein the first gate conductive layer spacers comprise a conductive material.
11. The device of claim 10 , wherein the conductive material is identical to the gate electrode.
12. The device of claim 10 , wherein the conductive material is a polysilicon.
13. The device of claim 6 , wherein the salicide layer is formed over a top surface of the first gate conductive layer spacers.
14. The device of claim 6 , wherein the salicide layer comprises at least one of Ti-based salicide, Co-based salicide, Ta-based salicide, and Ni-based salicide.