Semiconductor die with integrated electro-static discharge device
A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.
1. A semiconductor die, comprising:
a substrate;
a first layer, deposited on the substrate, which includes an electro-static discharge (ESD) device with at least a metal component coupled to an input/output (I/O) pad and coupled to a ground voltage via a signal line, wherein adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap, and wherein, when field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals; and
a second layer, deposited on the first layer, that at least partially encloses the ESD gap between the metal component and the I/O pad, thereby providing a gas in the ESD gap.
2. The semiconductor die of claim 1 , wherein a surface of the second layer and a surface of the substrate define a cavity that fully encloses the ESD gap.
3. The semiconductor die of claim 2 , wherein a gas in the cavity is other than air.
4. The semiconductor die of claim 1 , wherein the second layer includes an opening defined in part by a surface of the second layer that exposes the ESD gap to the gas.
5. The semiconductor die of claim 1 , wherein at least one of the adjacent edges has an arrow shape in a plane of the first layer.
6. The semiconductor die of claim 1 , wherein the adjacent edges both have an arrow shape in a plane of the first layer; and
wherein the spacing that defines the ESD gap is between tips of the arrow-shaped adjacent edges.
7. The semiconductor die of claim 1 , further comprising a third layer between the substrate and the first layer which is underneath at least the ESD gap.
8. The semiconductor die of claim 7 , wherein the third layer includes a dielectric.
9. The semiconductor die of claim 1 , further comprising multiple ESD devices in the first layer, wherein the metal component in a given one of the ESD devices is coupled to a corresponding I/O pad and is coupled to the ground voltage via the signal line.
10. The semiconductor die of claim 9 , wherein the ESD devices are arranged in a 2-dimensional array in the first layer.
11. The semiconductor die of claim 9 , wherein the ESD devices are arranged in a 1-dimensional array along the signal line in the first layer.
12. The semiconductor die of claim 9 , wherein a turn-on voltage of the given ESD device is in one of at least two ranges of voltages, which are separated by a threshold voltage.
13. The semiconductor die of claim 12 , wherein a size of the given ESD device corresponds to the turn-on voltage.
14. The semiconductor die of claim 1 , further comprising an ESD diode which is coupled in parallel with the ESD device.
15. The semiconductor die of claim 14 , further comprising a low-pass filter that couples the ESD device and the ESD diode.
16. The semiconductor die of claim 14 , wherein the ESD device has a lower capacitance than the ESD diode.