Method for forming an ultrathin Cu barrier/seed bilayer for integrated circuit device fabrication

1 . A method of manufacturing a diffusion barrier for copper metallization in an electronic device, the method comprising:

providing a copper layer and a dielectric layer within the electronic device; and

forming over the dielectric layer and the copper layer a single layer of an alloy, the alloy comprising a copper platable metal and a nitride forming material and nitrogen.

2 . The method as set forth in claim 1 further comprising: annealing the single layer of the alloy to form

a first layer positioned adjacent to a surface of the dielectric layer wherein the layer comprises the nitride forming material and the nitrogen, and

a second layer positioned adjacent to the first layer wherein the second layer comprises the copper platable metal.

3 . The method as set forth in claim 1 wherein the copper platable metal is selected from a group of metals that have an absolute Gibb's free energy formation of metal oxide that is less than that of copper oxide.

4 . The method as set forth in claim 1 wherein the copper platable metal is selected from a group of metals consisting of ruthenium, indium, osmium, platinum and rhodium.

5 . The method as set forth in claim 1 wherein the nitride forming material is selected from a group of nitride forming materials that have an absolute Gibb's free energy formation of metal nitride that is greater higher than that of silicon nitride.

6 . The method as set forth in claim 1 wherein the nitride forming material is selected from a group of materials consisting of tungsten, molybdenum and chromium.

7 . The method as set forth in claim 1 wherein the copper platable metal of the alloy comprises ruthenium and the nitride forming material comprises tungsten.

8 . The method as set forth in claim 7 further comprising:

annealing the single layer of the alloy; and

segregating the single layer of the alloy into

a first layer that comprises a barrier layer that is located adjacent to a surface of the dielectric layer wherein the barrier layer comprises tungsten and nitrogen, and

a second layer that is adjacent to the first layer wherein the second layer comprises ruthenium.

9 . The method as set forth in claim 8 wherein the annealing the single layer of the alloy comprises:

annealing the single layer of the alloy to a temperature between about two hundred degrees Celsius and about four hundred degrees Celsius.

10 . The method as set forth in claim 8 wherein the first layer comprises an amorphous tungsten nitride layer that has a thickness of less than about 2 nanometers.

11 . The method as set forth in claim 8 wherein the first layer comprises an amorphous tungsten nitride layer that retains nitrogen in solution when the alloy is heated.

12 . The method as set forth in claim 8 wherein the first layer comprises an amorphous tungsten nitride layer that is stable up to a temperature of seven hundred degrees Celsius.

13 . The method as set forth in claim 8 wherein the second layer comprises a ruthenium rich film that provides a seed layer for copper electrochemical plating.

14 . The method as set forth in claim 8 wherein the first layer comprises an amorphous tungsten nitride layer that prevents an expulsion of nitrogen from the first layer that delays a crystallization of the ruthenium in the second layer up to a temperature in a range of about five hundred degrees Celsius to about six hundred degrees Celsius.

15 . A method of manufacturing a diffusion barrier for copper metallization in an electronic device, the method comprising:

providing a dielectric layer within the electronic device; and

forming over the dielectric layer a single layer of an alloy comprising ruthenium and tungsten and nitrogen.

16 . The method as set forth in claim 15 further comprising:

annealing the single layer of the alloy to a temperature between about two hundred degrees Celsius and about four hundred degrees Celsius; and

segregating the single layer of the alloy into

a first layer that comprises a barrier layer that is located adjacent to a surface of the dielectric layer wherein the barrier layer comprises tungsten and nitrogen, and

a second layer that is adjacent to the first layer wherein the second layer comprises ruthenium.

17 . The method as set forth in claim 16 wherein the first layer comprises an amorphous tungsten nitride layer that has a thickness that is less than a thickness of a barrier layer that is formed by two separate deposition steps.

18 . The method as set forth in claim 16 wherein the first layer comprises an amorphous tungsten nitride layer that has an amorphous form that provides better diffusion barrier properties than a conventional columnar microstructure of a diffusion barrier that is formed by two separate deposition steps.

19 . A diffusion barrier structure for copper metallization in an electronic device having a copper layer, the diffusion barrier structure comprising:

a single layer of an alloy formed over the copper layer and a dielectric layer wherein the alloy includes a copper platable metal and a nitride forming material and nitrogen.

20 . A diffusion barrier structure as set forth in claim 19 wherein the single layer of the alloy is segregated into

a first layer that comprises a barrier layer that is located adjacent to a surface of the dielectric layer wherein the barrier layer comprises the nitride forming material and nitrogen; and

a second layer that that is adjacent to the first layer wherein the second layer comprises the copper platable material.

21 . A diffusion barrier structure as set forth in claim 20 wherein the copper platable material is ruthenium and the nitride forming material is tungsten.