Semiconductor reference voltage generating device
View Patent ↗A reference voltage generating circuit has more than two first wells each having a first impurity concentration and more than two second wells each having a second impurity concentration different from the first impurity concentration. A first group of MOS transistors has more than two MOS transistors formed in respective ones of the first wells. A second group of MOS transistors has More than two MOS transistors formed in respective ones of the second wells.
1. A reference voltage generating circuit for a semiconductor device, the reference voltage generating circuit comprising:
a first well having an impurity concentration;
an enhancement type MOS transistor formed in the first well;
a second well having an impurity concentration;
a depletion type MOS transistor formed in the second well; and
a third well formed in a portion of the depletion type MOS transistor and having an impurity concentration different from the impurity concentration of the second well.
2. A semiconductor device having the reference voltage generating circuit according to claim 1 .
3. A reference voltage generating circuit according to claim 1 , wherein the impurity concentration of the first well is the same as the impurity concentration of the second well.
4. A reference voltage generating circuit comprising:
a first well having an impurity concentration;
a first MOS transistor formed in the first well;
a second well having a second impurity concentration;
a second MOS transistor formed in the second well; and
a third well formed in a portion of the second MOS transistor and having an impurity concentration different from the impurity concentration of the second well.
5. A semiconductor device having the reference voltage generating circuit according to claim 4 .
6. A reference voltage generating circuit according to claim 4 , wherein the impurity concentration of the first well is the same as the impurity concentration of the second well.