Digital clock smoothing
A method for digital clock smoothing is provided. The method comprises: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block; (B) obtaining FIFO depth B by subtracting modulo B for each stored symbol a symbol output address from a symbol input address; (C) inputting FIFO depth B into a programmable look-up table (LUT); (D) obtaining a phase detector error signal; (E) scaling the phase detector error signal to obtain a scaled error factor; (F) adding the scaled error factor to a nominal phase step to obtain a phase update; (G) obtaining a smoothed symbol rate; and (H) reading out each output symbol from FIFO under control of an output FIFO address control register at the smoothed symbol rate.
1. A method for digital clock smoothing comprising:
(A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block;
(B) obtaining said FIFO depth B by subtracting modulo B for each stored symbol a symbol output address from a symbol input address;
(C) inputting said FIFO depth B into a programmable Look Up Table (LUT);
(D) obtaining a phase detector error signal;
(E) scaling said phase detector error signal to obtain a scaled error factor, wherein said scaled error factor is normalized by using a set of parameters selected from the group consisting of: {a ratio of an input symbol rate to a reference clock; and a damping factor configured to compensate for latency of a frequency lock loop (FLL)};
(F) adding said scaled error factor to a nominal phase step to obtain a phase update;
(F1) computing said nominal phase step by using a nominal symbol rate, a modulation index, and a reference frequency;
(G) obtaining a smoothed symbol rate; and
(H) reading out each output symbol from said FIFO under control of an output FIFO address control register at said smoothed symbol rate.
2. The method of claim 1 , wherein said step (F1) further comprises:
(F1, 1) selecting said modulation index for BPSK modulation.
3. The method of claim 1 , wherein said step (F1) further comprises:
(F1, 2) selecting said modulation index for QPSK modulation.
4. A method for digital clock smoothing comprising:
(A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block;
(B) obtaining said FIFO depth B by subtracting modulo B for each stored symbol a symbol output address from a symbol input address;
(C) inputting said FIFO depth B into a programmable Look Up Table (LUT);
(D) obtaining a phase detector error signal;
(E) scaling said phase detector error signal to obtain a scaled error factor, wherein said scaled error factor is normalized by using a set of parameters selected from the group consisting of: {a ratio of an input symbol rate to a reference clock; and a damping factor configured to compensate for latency of a frequency lock loop (FLL)};
(F) adding said scaled error factor to a nominal phase step to obtain a phase update;
(F2) limiting said nominal phase step;
(G) obtaining a smoothed symbol rate; and
(H) reading out each output symbol from said FIFO under control of an output FIFO address control register at said smoothed symbol rate.
5. The method of claim 4 , wherein said step (F2) further comprises:
(F2, 1) creating limit masks.
6. The method of claim 4 , wherein said step (F2) further comprises:
(F2, 2) creating a positive limit mask.
7. The method of claim 4 , wherein said step (F2) further comprises:
(F2, 3) creating a negative limit mask.