Vertical-type semiconductor device and method of manufacturing the same
A vertical-type semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a wordline structure on the cell region of the semiconductor substrate, the wordline structure including a plurality of wordlines stacked on top of each other, a semiconductor structure through the wordline structure, a gate dielectric between the wordline structure and the semiconductor structure, and a dummy wordline structure on the peripheral circuit region, the dummy wordline structure having a vertical structure and including same components as the wordline structure.
1. A vertical-type semiconductor device, comprising:
a semiconductor substrate having a cell region and a peripheral circuit region;
a wordline structure on the cell region of the semiconductor substrate, the wordline structure including a plurality of wordlines stacked on top of each other;
a semiconductor structure through the wordline structure;
a gate dielectric between the wordline structure and the semiconductor structure; and
a dummy wordline structure on the peripheral circuit region, the dummy wordline structure having a vertical structure and including same components as the wordline structure.
2. The vertical-type semiconductor device as claimed in claim 1 , wherein top surfaces of the dummy wordline structure and the wordline structure are substantially level.
3. The vertical-type semiconductor device as claimed in claim 2 , wherein the dummy wordline structure and the wordline structure have a substantially same height along a vertical direction.
4. The vertical-type semiconductor device as claimed in claim 1 , wherein the dummy wordline structure surrounds the cell region.
5. The vertical-type semiconductor device as claimed in claim 1 , further comprising a dampproofing structure in the dummy wordline structure.
6. The vertical-type semiconductor device as claimed in claim 5 , wherein the dampproofing structure is within a through hole, the through hole passing vertically through the dummy wordline structure.
7. The vertical-type semiconductor device as claimed in claim 5 , wherein the dampproofing structure extends through an entire height of the dummy wordline structure.
8. The vertical-type semiconductor device as claimed in claim 7 , wherein the dampproofing structure surrounds the cell region.
9. The vertical-type semiconductor device as claimed in claim 5 , wherein the dampproofing structure includes a silicon nitride layer.
10. The vertical-type semiconductor device as claimed in claim 1 , further comprising:
a string select line structure on the wordline structure; and
a dummy string select line structure on the dummy wordline structure, top surfaces of the string select line structure and dummy string select line structure being substantially level.
11. The vertical-type semiconductor device as claimed in claim 1 , wherein the dummy wordline structure is disposed at an edge portion of the peripheral circuit region farthest from the cell region.
12. The vertical-type semiconductor device as claimed in claim 1 , further comprising a ground select structure between the wordline structure and the semiconductor substrate.
13. The vertical-type semiconductor device as claimed in claim 1 , wherein the wordline structure has a stepped shape.
14. The vertical-type semiconductor device as claimed in claim 1 , wherein the wordline structure, the semiconductor structure, and the gate dielectric define a vertical-type NAND flash memory connected in series.
15. A method for manufacturing a vertical-type semiconductor device, the method comprising:
forming a wordline structure on a cell region of a semiconductor substrate, the wordline structure including a plurality of wordlines stacked on top of each other;
forming a semiconductor structure through the wordline structure;
forming a gate dielectric between the wordline structure and the semiconductor structure; and
forming a dummy wordline structure on a peripheral circuit region of the semiconductor substrate, the dummy wordline structure having a vertical structure and including same components as the wordline structure.
16. The method as claimed in claim 15 , further comprising:
forming a plurality of stacked wordline conductive layers in the cell region and peripheral circuit region of the semiconductor substrate;
patterning the wordline conductive layers of the cell region to form the wordline structure; and
patterning the wordline conductive layers of the peripheral circuit region to form the dummy wordline structure, such that top surfaces of the dummy wordline structure and the wordline structure are substantially level.
17. The method as claimed in claim 15 , further comprising forming a dampproofing structure through the dummy wordline structure.
18. The method as claimed in claim 17 , wherein the dampproofing structure is formed of a silicon nitride layer.