Array substrate for a liquid crystal display device having multi-layered metal line and fabricating method thereof

1. A fabricating method of an array substrate for a liquid crystal display device, comprising:

forming a gate electrode and a gate line on a substrate;

forming a gate insulating layer on the gate electrode and the gate line;

forming an active layer on the gate insulating layer;

forming an ohmic contact layer on the active layer;

depositing a first metal layer of a multiple metal layer on the ohmic contact layer, wherein the first metal layer has a thickness within a range of about 100 Å to about 1000 Å;

plasma-treating the first metal layer;

sequentially depositing the other metal layers of the multiple metal layer on the first metal layer;

patterning the multiple metal layer to form source and drain electrodes and a data line;

forming a passivation layer on the source and drain electrodes and the data line; and

forming a pixel electrode on the passivation layer.

2. The method according to claim 1 , wherein the plasma-treating the first metal layer is performed using an oxygen (O 2 ) plasma.

3. The method according to claim 2 , wherein the plasma-treating the first metal layer is performed using one of direct current (DC) plasma, radio frequency (RF) plasma and a combination of DC plasma and RF plasma.

4. The method according to claim 1 , wherein the multiple metal layer comprises first, second and third metal layers.

5. The method according to claim 4 , wherein the first metal layer includes one of titanium (Ti), chromium (Cr), tantalum (Ta), molybdenum (Mo), molybdenum tungsten (MoW), and an alloy thereof.

6. The method according to claim 5 , wherein the second metal layer includes one of aluminum (Al) and aluminum (Al) alloy.

7. The method according to claim 6 , wherein the third metal layer includes molybdenum (Mo).

8. A fabricating method of an array substrate for a liquid crystal display device, comprising:

forming a gate electrode and a gate line on a substrate;

forming a gate insulating layer on the gate electrode;

forming an active layer on the gate insulating layer;

forming an ohmic contact layer on the active layer;

sequentially depositing a first metal layer of chromium (Cr), a second metal layer of aluminum (Al) and a third metal layer of molybdenum (Mo) on the ohmic contact layer, wherein the first metal layer has a thickness within a range of about 30 Å to about 1000 Å, the second metal layer has a thickness within a range of about 1000 Å to about 3000 Å, and the third metal layer has a thickness within a range of about 30 Å to about 1000 Å;

patterning the first, second and third metal layers to form source and drain electrodes and a data line crossing the gate line;

forming a passivation layer on the source and drain electrodes and the data line; and

forming a pixel electrode on the passivation layer.

9. The method according to claim 8 , wherein patterning the first, second and third metal layers comprises:

etching an entire surface of the third metal layer;

forming a photoresist (PR) pattern on the second metal layer; and

sequentially etching the second and first metal layers using the PR pattern as an etching mask.

10. The method according to claim 9 , wherein etching an entire surface of the third metal layer is performed by using a first solution including hydrogen peroxide (H 2 O 2 ).

11. The method according to claim 10 , wherein etching the second metal layer is performed by using a second solution of mixed acid solution.

12. The method according to claim 11 , wherein etching the first metal layer is performed by using a third solution including Ce(NH 4 ) 2 (NO 3 )+HNO 3 (CAN).