I/O link with configurable forwarded and derived clocks
An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.
1. A chip comprising:
a first circuit operable to generate a derived clock signal from a data signal;
a forwarded clock signal circuit operable to receive a forwarded clock signal corresponding to the data signal;
a second circuit operable to receive the derived clock signal and the forwarded clock signal, and to output an output clock signal based on either the derived clock signal or the forwarded clock signal; and
a third circuit operable to receive the output clock signal and to adjust its phase, the third circuit to generate a sampling clock signal to sample the data signal.
2. The chip of claim 1 , comprising a fourth circuit to phase align the sampling clock signal.
3. The chip of claim 2 , wherein the fourth circuit comprises a phase interpolator.
4. The chip of claim 2 , wherein the forwarded clock circuit is coupled to a delay locked loop (DLL).
5. The chip of claim 2 , wherein the first circuit is operable to observe transitions of the data signal to generate the derived clock signal.
6. The chip of claim 3 further comprises an interpolation controller which is operable to control the phase interpolator.
7. The chip of claim 4 , wherein the DLL is coupled to a second selector unit.
8. The chip of claim 1 , wherein both the first circuit and the forwarded clock signal circuit are coupled to a first selector circuit, wherein the first selector circuit is operable to provide a selected clock signal to a phase locked loop (PLL).
9. The chip of claim 1 , wherein the second circuit comprises a phase locked loop (PLL) and a delay locked loop (DLL), the outputs of the PLL and the DLL provided as input to a second selector unit.
10. The chip of claim 9 , wherein the PLL is operable to oscillate at a frequency determined by a frequency of the data signal.
11. The chip of claim 1 further comprises a data receiver which is operable to receive the data signal and to sample the data signal with the sampling clock signal to generate a clocked data signal.
12. The chip of claim 11 , wherein the data receiver is coupled to the third circuit.
13. The chip of claim 11 further comprises a loop filter to receive the clocked data signal.
14. The chip of claim 13 further comprises an up/down circuit coupled to the loop filter, the up/down circuit to generate a signal indicating a direction of a signal output from the loop filter.