Granted Patent B2

US 8,250,420 · App. 12/594,594 · Granted Aug 21, 2012

Abstract

Claims (30)

1. An integrated circuit comprising:

a circuit portion having a plurality of inputs and a plurality of outputs, the plurality of inputs being arranged to receive a test pattern in a test mode of the integrated circuit, the test pattern comprising a plurality of test vectors for feeding to the plurality of inputs in successive clock cycles; and

a test arrangement for testing the circuit portion, the test arrangement comprising:

a test pattern generator for generating the test pattern;

masking logic for masking selected outputs of the plurality of outputs; and

a signal generator coupled to the masking logic, the signal generator for generating a masking signal triggering the masking of all of said circuit portion outputs only during selected cycles of the successive clock cycles, the signal generator being responsive to clock cycle selection data.

2. An integrated circuit as claimed in claim 1 , wherein the signal generator comprises a clock cycle counter and a comparator for comparing the clock cycle selection data with the clock cycle counter value.

3. An integrated circuit as claimed in claim 2 , wherein the clock cycle selection data comprises a plurality of bits, the clock cycle counter comprises a plurality of counter bits and the comparator comprises a plurality of logic gates, each logic gate being configured to compare a clock cycle selection data bit with a corresponding counter bit, the signal generator being configured to generate the masking signal when at least one of the clock cycle selection data bits matches the corresponding counter bit.

4. An integrated circuit as claimed in claim 1 , further comprising means for inverting the masking signal.

5. An integrated circuit as claimed in claim 4 , wherein said means comprise an exclusive logic gate being responsive to the masking signal and an inversion signal.

6. An integrated circuit as claimed in claim 1 , wherein the test arrangement further comprises a memory device for storing a plurality of multi-bit masks, the masking logic being configurable by said masks, the memory device being responsive to mask selection data.

7. An integrated circuit as claimed in claim 6 , wherein the test arrangement further comprises a plurality of logic gates coupled between the memory device and the masking logic such that each logic gate is responsive to one bit from a multi-bit mask, each logic gate further being responsive to the masking signal.

8. An integrated circuit as claimed in claim 6 , wherein the memory device is responsive to a further inversion signal for inverting a multi-bit mask selected by the mask selection data.

9. An integrated circuit as claimed in claim 6 , wherein the masking logic comprises a mask generator for generating further multi-bit masks in response to compressed masking data (m 1 -m n ), the masking logic further comprising a plurality of logic gates, each logic gate having its inputs coupled to one bit of a multi-bit mask and to one bit of a further multi-bit mask respectively.

10. An integrated circuit as claimed in claim 9 , wherein the masking logic further comprises a further plurality of logic gates coupled between the plurality of logic gates of the masking logic and the mask generator, each logic gate of the further plurality of logic gates having its inputs coupled to a bit from a further multi-bit mask and a mask enable signal respectively.

11. An integrated circuit as claimed in claim 1 , further comprising a further memory device for storing a plurality of test configuration words, each of said words comprising: the clock cycle selection data; a bit specifying the inversion signal; the mask selection data; a further bit specifying the further inversion signal; and the compressed mask selection data.

12. An integrated circuit as claimed in claim 1 , further comprising an output coupled to the masking logic via data compression logic.

13. A method of generating test data for an integrated circuit as claimed in claim 1 , the method comprising:

generating a test pattern for feeding to the plurality of inputs over a plurality of clock cycles;

determining the expected responses to the test pattern on the plurality of outputs, the expected responses including undefined values;

determining, for said test pattern, the clock cycles in which all outputs from said plurality of outputs need masking;

generating clock cycle selection data for configuring the signal generator to generate the masking signal in the determined clock cycles; and

generating masking data for the undefined values in unmasked clock cycles.

14. A method as claimed in claim 13 , further comprising generating an inversion bit for inverting the masking signal.

15. A method as claimed in claim 13 , wherein the step of determining the clock cycles in which all outputs from said plurality of outputs need masking further comprises:

determining the outputs that need masking during all clock cycles;

providing a mask for masking said determined outputs; and

storing said mask in a memory device of the integrated circuit.

16. A method as claimed in claim 15 , wherein the step of determining the clock cycles in which all outputs from said plurality of outputs need masking and the step of determining the outputs that need masking during all clock cycles are executed in combination with the objective to minimize the masking of expected responses having defined values.

17. An automated test pattern generation tool implementing the steps of the method as claimed in claim 13 .

Assignments (12)