IP Library Granted Patent US 8,907,430
Granted Patent B2
US 8,907,430 · App. 12/599,431 · Granted Dec 9, 2014

Semiconductor device and manufacturing method of semiconductor device

Inventors: Akihiro Usujima (Kawasaki, JP); Junichi Ariyoshi (Kawasaki, JP); Taiji Ema (Kawasaki, JP)
Assignee: Fujitsu Semiconductor Limited
H01L27/11526H01L21/28273H01L21/823418H01L21/823456H01L21/823462H01L21/823468H01L27/105H01L27/11546H01L29/7881
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Quick Facts
Patent No.
US 8,907,430
App. No.
12/599,431
Granted
Dec 9, 2014
Kind
B2
Abstract

A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film.

Claims (32)

1. A semiconductor device comprising:

a first transistor including a first gate side wall insulating film and a second gate side wall insulating film disposed outside of the first gate side wall insulating film;

a second transistor including a third gate side wall insulating film that has the same composition as a composition of the first gate side wall insulating film, and a fourth gate side wall insulating film that has the same composition as a composition of the second gate side wall insulating film, the fourth gate side wall insulating film being disposed outside of the third gate side wall insulating film; and

a third transistor including a fifth gate side wall insulating film that has the same composition as the composition of the second gate side wall insulating film and the fourth gate side wall insulating film, wherein

a total side wall spacer width of the third transistor is smaller than a total side wall spacer width of the second transistor by a thickness corresponding to the third gate side wall insulating film;

wherein the first transistor is a flash memory;

wherein the second transistor is configured to operate at a higher voltage than the third transistor;

wherein each of the first gate side wall insulating film and the third gate side wall insulating film contains a first silicon oxide film and a first silicon nitride film which is disposed outside of the first silicon oxide film;

wherein each of the second gate side wall insulating film, the fourth gate side wall insulating film, and the fifth gate side wall insulating film contains a second silicon oxide film and a second silicon nitride film which is disposed outside of the second silicon oxide film; and

wherein the first silicon oxide film has a higher density than the second silicon oxide film, and the first silicon nitride film has a higher density than the second silicon nitride film.

2. A semiconductor device comprising:

a first transistor including a first gate side wall insulating film and a second gate side wall insulating film disposed outside of the first gate side wall insulating film;

a second transistor including a third gate side wall insulating film that has the same composition as a composition of the first gate side wall insulating film, and a fourth gate side wall insulating film that has the same composition as a composition of the second gate side wall insulating film, the fourth gate side wall insulating film being disposed outside of the third gate side wall insulating film; and

a third transistor including a fifth gate side wall insulating film that has the same composition as the composition of the second gate side wall insulating film and the fourth gate side wall insulating film, wherein

a total side wall spacer width of the third transistor is smaller than a total side wall spacer width of the second transistor by a thickness corresponding to the third gate side wall insulating film;

wherein the first transistor is a flash memory;

wherein the second transistor is configured to operate at a higher voltage than the third transistor;

wherein each of the second gate side wall insulating film, the fourth gate side wall insulating film, and the fifth gate side wall insulating film is formed by a combination of a TEOS film and a nitride film;

wherein the nitride film is disposed outside of the TEOS film;

wherein the nitride film covers the TEOS film;

wherein each of the first gate side wall insulating film and the third gate side wall insulating film is formed by a combination of a thermally-oxidized film and a nitride film.

3. A semiconductor device comprising:

a first transistor including a first gate insulating film and a first gate side wall insulating film and a second gate side wall insulating film disposed outside of the first gate side wall insulating film;

a second transistor including a second gate insulating film and a third gate side wall insulating film that has the same composition as a composition of the first gate side wall insulating film, and a fourth gate side wall insulating film that has the same composition as a composition of the second gate side wall insulating film, the fourth gate side wall insulating film being disposed outside of the third gate side wall insulating film; and

a third transistor including a fifth gate side wall insulating film that has the same composition as the composition of the second gate side wall insulating film and the fourth gate side wall insulating film, wherein

a total side wall spacer width of the third transistor is smaller than a total side wall spacer width of the second transistor by a thickness corresponding to the third gate side wall insulating film,

wherein the first transistor is a flash memory,

wherein the second gate insulating film of the second transistor has a film thickness that is larger than a film thickness of the first gate insulating film of the first transistor,

wherein each of the second gate side wall insulating film, the fourth gate side wall insulating film, and the fifth gate side wall insulating film is formed by a combination of a TEOS film and a nitride film,

wherein the nitride film is disposed outside of the TEOS film; and

wherein the nitride film covers the TEOS film;

wherein each of the first gate side wall insulating film and the third gate side wall insulating film is formed by a combination of a thermally-oxidized film and a nitride film.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2009
From: USUJIMA, AKIHIRO; ARIYOSHI, JUNICHI; EMA, TAIJI
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 023503/0238 →
Continuity (2)
Continuation PCTJP2007064998 · Jul 31, 2007
Related Publication 20100308420A1 · Dec 9, 2010