Semiconductor memory including voltage detection circuit for generating sense amplifier signal

1. A semiconductor memory, comprising:

a plurality of memory cells each having a capacitor capable of storing an electric charge corresponding to a logic of data;

bit lines coupled to each of the memory cells;

a voltage detection circuit being provided corresponding to a pair of the bit lines from which complementary data are read, and outputting a detection signal when an amount of charges read to one of the pair of the bit lines reaches a predetermined amount when the memory cells are accessed;

a timing generator having a plurality of cascade-coupled delay circuits, outputting timing signals from each of the delay circuits, and outputting a sense amplifier activation signal in response to one of the timing signals; and

a sense amplifier determining logics of data read to the bit lines from the memory cells in synchronization with the sense amplifier activation signal, wherein

the timing generator comprises a mask circuit masking an output of the sense amplifier activation signal until the detection signal is output, and

a delay circuit in a next stage of one of the delay circuits outputting the one of the timing signals operates upon reception of the sense amplifier activation signal.

2. A semiconductor memory, comprising:

a plurality of memory cells each having a capacitor capable of storing an electric charge corresponding to a logic of data;

bit lines coupled to each of the memory cells;

a voltage detection circuit being provided corresponding to a pair of the bit lines from which complementary data are read, and outputting a detection signal when information indicating an amount of charges read to one of the pair of the bit lines reached a predetermined amount is received;

a timing generator having a plurality of cascade-coupled delay circuits, outputting timing signals from each of the delay circuits, and outputting a sense amplifier activation signal in response to either one of the detection signal and one of the timing signals, whichever be output earlier; and

a sense amplifier determining logics of data read to the bit lines from the memory cells in synchronization with the sense amplifier activation signal.

3. The semiconductor memory according to claim 1 , further comprising

pre-sense amplifiers being coupled to each of the bit lines and amplifying voltage amplitude of data read from the memory cells via the bit lines, wherein

the voltage detection circuit is coupled to a pair of the pre-sense amplifiers amplifying complementary data, and outputs the detection signal when a voltage value of data amplified by one of the pair of the pre-sense amplifiers reaches a first voltage when the memory cells are accessed, and

the sense amplifier determines logics read to the bit lines from the memory cells upon reception of data amplified by the pre-sense amplifiers.

4. The semiconductor memory according to claim 3 , wherein

the pre-sense amplifiers each comprises:

a charge transferring circuit coupled to the bit lines;

a charge storing circuit being coupled to the bit lines via the charge transferring circuit, storing a charge read to the bit lines from the memory cells in a read operation, and generating a read voltage according to a stored charge; and

a control circuit controlling a charge transfer capability of the charge transferring circuit according to a change in voltage of the bit lines caused by a read charge so as to transfer a charge read to the bit lines to the charge storing circuit; and wherein

the control circuit comprises:

an inverter having an input coupled to the bit lines and an output coupled to a control terminal of the charge transferring circuit; and

a switch circuit which turns on in response to start of the read operation so as to couple a power supply terminal of the inverter to a power supply line and turns off in response to an output of the sense amplifier activation signal.

5. The semiconductor memory according to claim 1 , further comprising

a delay circuit outputting a time-out signal at a predetermined time after data is read from the memory cells to the bit lines, wherein

the mask circuit comprises a mask release circuit releasing a mask in response to an output of the time-out signal, so as to output the sense amplifier activation signal also when the detection signal is not output.

6. The semiconductor memory according to claim 1 , further comprising:

a plate line which is coupled to one end of the capacitor and to which a high voltage is applied during a read operation; and

a plate driver which is arranged in an arrangement direction of the bit lines with neighboring a memory cell array and which applies a voltage to the plate line, wherein

the voltage detection circuit is provided corresponding to a bit line that is on a far side from the plate driver.

7. The semiconductor memory according to claim 1 , wherein the capacitor is a ferroelectric capacitor.

8. The semiconductor memory according to claim 1 , wherein

the memory cells each comprises a pair of capacitors being coupled to one of pairs of the bit lines and storing electric charges corresponding to inverted logics from each other, and

the voltage detection circuit is provided corresponding to the one of the pairs of the bit lines.

9. The semiconductor memory according to claim 1 , wherein

at least two of the memory cells are a first reference memory cell retaining a first logic in the capacitor and a second reference memory cell retaining a second logic that is an inverse of the first logic in the capacitor,

remaining ones of the memory cells are real memory cells retaining data,

the real memory cells each comprises one capacitor coupled to the bit lines and capable of storing an electric charge corresponding to a logic of data,

the voltage detection circuit is provided corresponding to the first and second reference memory cells, and

the sense amplifier determines a logic of data retained in each of the real memory cells with reference to a pair of voltage values corresponding to charges read from each of the first and second reference memory cells.

10. The semiconductor memory according to claim 1 , wherein

the voltage detection circuit comprises:

a CMOS inverter receiving an enable signal set to high logic level in a read operation through an input and outputting a detection signal from an output; and

a detection transistor of nMOS type coupled between a source of an nMOS transistor of the CMOS inverter and a ground line, and a gate of the detection transistor is coupled to an output of the pre-sense amplifier, wherein

the first voltage is a threshold voltage of the detection transistor.

11. The semiconductor memory according to claim 1 , wherein

the voltage detection circuit comprises an inverter of schmitt trigger type which detects amounts of charges read to the bit lines.