Thin film transistor array substrate and manufacturing method thereof
View Patent ↗A thin film transistor array substrate includes a gate line disposed on a substrate, the gate line comprising a gate electrode including a lower film and an upper film thicker than the lower film, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, an ohmic contact layer formed on the semiconductor layer, a data line electrically connected to a source electrode and a drain electrode formed on the ohmic contact layer, the lower film of the gate line is in contact with the gate insulating layer at a crossing portion of the gate line and the data line and the heights of the source electrode and the drain electrode are substantially the same as or less than a height of the semiconductor layer.
1. A thin film transistor array substrate comprising:
a gate line disposed on a substrate, the gate line comprising a gate electrode including a lower film and an upper film thicker than the lower film;
a gate insulating layer formed on the gate line;
a semiconductor layer formed on the gate insulating layer;
an ohmic contact layer formed on the semiconductor layer;
a source electrode and a drain electrode formed on the ohmic contact layer, the source electrode and the drain electrode having heights substantially the same as or less than a height of the semiconductor layer; and
a data line electrically connected to the source electrode and the drain electrode, the data line crossing the gate line at a crossing portion, and the lower film of the gate line contacting the gate insulating layer at the crossing portion.
2. The thin film transistor array substrate of claim 1 , wherein a thickness of the data line at the crossing portion of the gate line and the data line is d, a thickness of the ohmic contact layer is n, and a thickness of the upper film of the gate line is t, and d, n and t have the following relation:
d+n<t.
3. The thin film transistor array substrate of claim 1 , wherein planar shapes of the semiconductor layer and the ohmic contact layer are substantially the same as the data line, the source electrode and the drain electrode.
4. The thin film transistor array substrate of claim 1 , further comprising:
a passivation layer on the data line;
a contact hole formed in the passivation layer; and
a pixel electrode electrically connected to the drain electrode through the contact hole.
5. The thin film transistor array substrate of claim 4 , wherein:
the passivation layer comprises at least one of an organic material and color filter material.
6. The thin film transistor array substrate of claim 4 , wherein the pixel electrode overlaps with the semiconductor layer.
7. The thin film transistor array substrate of claim 1 , the source electrode and the drain electrode overlap with the gate electrode on a sidewall of the gate electrode.