Thin film transistor panel and fabricating method thereof
View Patent ↗A thin film transistor panel includes; an insulating substrate, a gate line including a gate electrode disposed on the insulating substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer, the semiconductor layer including a sidewall, a data line including a source electrode disposed on the semiconductor layer, a drain electrode disposed substantially opposite to and spaced apart from the source electrode, a first protective film disposed on the data line, the first protective film including a sidewall, a second protective film disposed on the first protective film and including a sidewall, and a pixel electrode electrically connected to the drain electrode, wherein the sidewall of the second protective film is disposed inside an area where the sidewall of the first protective film is disposed, and the source electrode and the drain electrode cover the sidewall of the semiconductor layer.
1. A method for manufacturing a thin film transistor panel, the method comprising;
disposing a gate line including a gate electrode and a gate pad on an insulating substrate;
disposing a gate insulating layer on the gate line;
disposing a semiconductor layer on the gate insulating layer;
disposing a data line including a source electrode on the semiconductor layer and a data pad;
disposing a drain electrode spaced apart from the source electrode with respect to the gate electrode on the semiconductor layer;
disposing a first insulating layer and a second insulating layer on the data line and the drain electrode;
etching the first insulating layer and the second insulating layer to form a second protective film, a first protective film having a sidewall which protrudes beyond the second protective film and a first contact hole which exposes a portion of the drain electrode; and
disposing a pixel electrode electrically connected to the drain electrode.
2. The method of claim 1 , wherein forming the semiconductor layer comprises:
depositing an amorphous silicon layer on the gate insulating layer;
depositing an amorphous silicon layer doped with impurity on the amorphous silicon layer;
disposing a first photo-resist pattern and a second photo-resist pattern thinner than the first photo-resist pattern on the amorphous silicon and the amorphous silicon doped with impurity;
exposing the gate pad by removing the amorphous silicon, the amorphous silicon doped with impurity, and the gate insulating layer using the first photo-resist pattern and the second photo-resist pattern as an etching mask;
exposing the amorphous silicon doped with impurity by removing the second photo-resist pattern;
exposing the gate insulating layer by etching the amorphous silicon doped with impurity and the amorphous silicon using the first photo-resist pattern as an etching mask; and
removing the first photo-resist pattern.
3. The method of claim 2 , wherein disposing the data line and the drain electrode on the semiconductor layer comprises disposing an interconnector on the gate pad.
4. The method of claim 3 , wherein forming the second protective film and the first protective film comprises;
disposing a third photo-resist pattern and a fourth photo-resist pattern thinner than the third photo-resist pattern on the second insulating layer;
exposing the interconnector and the data pad by etching the second insulating layer and the first insulating layer using the third photo-resist pattern and the fourth photo-resist pattern as an etching mask.
5. The method of claim 4 , wherein forming the second protective film and the first protective film comprises;
removing the fourth photo-resist pattern;
etching the second insulating layer using the third photo-resist pattern as an etching mask to expose the first protective film, and etching a portion of the second insulating layer under the third photo-resist pattern to form an undercut.
6. The method of claim 5 , wherein disposing the pixel electrode electrically connected to the drain electrode comprises:
disposing a transparent conductive layer on the third photo-resist pattern and the first protective film; and
removing the third photo-resist pattern.
7. The method of claim 6 , further comprising using an etching gas which has a greater etching rate with respect to the second insulating layer than an etching rate with respect to the first insulating layer to form the undercut.
8. The method of claim 7 , wherein the etching gas has an etching rate with respect to the second insulating layer which is about three times to about five times greater than an etching rate with respect to the first insulating layer.
9. The method of claim 6 , wherein disposing the pixel electrode comprises disposing a contact assistant on the interconnector and the data pad.
10. A method for manufacturing a thin film transistor panel, the method comprising;
disposing a gate line, the gate line including a gate electrode and a gate pad, on an insulating substrate;
disposing a first insulating layer on the gate line;
disposing a semiconductor layer on the first insulating layer;
exposing a gate pad through the first insulating layer;
forming a data line including a source electrode disposed on the semiconductor layer, a data pad disposed on the first insulating layer, a drain electrode disposed substantially opposite the source electrode with respect to the gate electrode, and an interconnector disposed on the exposed gate pad;
disposing a second insulating layer and a third insulating layer on the data line and the drain electrode;
etching the third insulating layer and the second insulating layer to form a contact hole which exposes a portion of the drain electrode; and
disposing a pixel electrode electrically connected to the drain electrode.