High speed receive equalizer architecture
View Patent ↗Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.
1. An apparatus comprising:
a continuous time filter configured to filter a signal to provide a filtered signal to a summer;
the summer configured to combine the filtered signal with feedback signals received from a decision feedback equalizer to generate a soft decision signal and provide the soft decision signal to the decision feedback equalizer and an adaptation circuit;
the decision feedback equalizer configured to receive the soft decision signal from the summer and to provide equalized data signals to a clock and data recovery circuit based on the soft decision signal and to provide the feedback signals to the summer;
the clock and data recovery circuit configured to generate an extracted clock signal from at least a portion of the equalized data signals based on a delay adjust signal received from an adaptation circuit; and
the adaptation circuit configured to provide the delay adjust signal to the clock and data recovery circuit and adjust the delay adjust signal based on a mean square error of the soft decision signal received from the summer.
2. The apparatus of claim 1 , wherein the adaptation circuit is configured to adapt the equalization according to at least one dithering algorithm by adjusting the delay adjust signal based on a change of the mean square error of the soft decision signal.
3. The apparatus of claim 1 , wherein the adaptation circuit is configured to adapt the equalization according to at least one dithering algorithm by adjusting the delay adjust signal in a same direction as a previous adjustment if a mean square error of the soft decision signal decreases and adjusting the delay adjust signal in an opposite direction from the previous adjustment if the mean square error of the soft decision signal increases.
4. The apparatus of claim 1 , wherein the decision feedback equalizer comprises a retimer configured to generate recovered equalized data signals from the equalized data signals in response to the extracted clock signal.
5. The apparatus of claim 1 , further comprising a variable gain amplifier configured to receive an input data and a control signal, the variable gain amplifier being configured to amplify the input data signal based on the control signal to provide the signal to the continuous time filter.
6. The apparatus of claim 1 , further comprising:
a variable gain amplifier configured to receive an input data signal from outside the apparatus and a control signal from an automatic gain control circuit, the variable gain amplifier being configured to amplify the input data signal based on the control signal to provide the signal to the continuous time filter; and
the automatic gain control circuit configured to receive the filtered signal from the continuous time filter and to provide the control signal to the variable gain amplifier based on the control signal.
7. The apparatus of claim 1 , further comprising a demultiplexer configured to receive the equalized data signals from the decision feedback equalizer and demultiplex the recovered equalized data into a plurality of signals each having a data rate lower than the signal filtered by the continuous time filter.
8. The apparatus of claim 1 , wherein:
the continuous time filter is configured to filter the signal based on a bandwidth adjust signal received from the adaptation circuit; and
the adaptation circuit is configured to provide the bandwidth adjust signal to the continuous time filter and to modify the bandwidth adjust signal based on the mean square error of the soft decision signal.
9. An apparatus comprising:
a continuous time filter coupled to an adaptation circuit, the continuous time filter being configured to filter a signal based on a bandwidth adjust signal received from the adaptation circuit to provide a filtered signal to a summer;
the summer configured to combine the filtered signal with feedback signals received from a decision feedback signal received from a decision feedback equalizer to generate a soft decision signal and provide the soft decision signal to the decision feedback equalizer and an adaptation circuit;
the decision feedback equalizer configured to receive the filtered soft decision signal from the summer and to provide equalized data signals to a clock and data recovery circuit based on the soft decision signal and to provide the feedback signals to the summer, the decision feedback equalizer including a retimer configured to generate recovered equalized data signals from the equalized data signals in response to receiving an extracted clock signal from the clock and data recovery circuit;
the clock and data recovery circuit configured to generate the extracted clock signal from at least a portion of the equalized data signals based on a delay adjust signal received from the adaptation circuit and provide the extracted clock signal to the decision feedback equalizer; and
the adaptation circuit configured to provide the bandwidth adjust signal to the continuous time filter and the delay adjust signal to the clock and data recovery circuit and to adjust at least one of the bandwidth adjust signal and the delay adjust signal based on a mean square error of the soft decision signal received from the summer.
10. The apparatus of claim 9 , wherein the adaptation circuit is configured to adjust at least one of the bandwidth adjust signal and the delay adjust signal based on the mean square error of the soft decision signal according to at least one dithering algorithm.
11. The apparatus of claim 9 , wherein the adaptation circuit is configured to adjust at least one of the bandwidth adjust signal and the delay adjust signal based on the mean square error of the soft decision signal according to at least one dithering algorithm by adjusting at least one of the bandwidth adjust signal and the delay adjust signal in a same direction as a previous adjustment if the mean square error of the soft decision signal decreases and adjusting the at least one of the bandwidth adjust signal and the delay adjust signal in an opposite direction from the previous adjustment if the mean square error of the soft decision signal increases.
12. The apparatus of claim 9 , further comprising an analog to digital converter configured to provide a digital signal to the decision feedback equalizer based on the soft decision signal provided to the analog to digital converter by the summer.
13. The apparatus of claim 9 , further comprising a variable gain amplifier configured to receive an input signal from outside the apparatus and a control signal from an automatic gain control circuit, the variable gain amplifier being configured to amplify the input signal based on the control signal to provide the signal to the continuous time filter.
14. The apparatus of claim 9 , further comprising:
a variable gain amplifier configured to receive an input signal from outside the apparatus and a control signal from an automatic gain control circuit, the variable gain amplifier being configured to amplify the input signal based on the control signal to provide the signal to the continuous time filter; and
the automatic gain control circuit configured to receive the filtered signal from the continuous time filter and to provide the control signal to the variable gain amplifier based on the filtered signal.
15. The apparatus of claim 9 , further comprising a delay lock loop configured to generate a clock signal from the extracted clock signal.
16. An apparatus comprising:
a decision feedback equalizer configured to receive a signal and to generate equalized data signals based on the signal;
a clock and data recovery circuit coupled to the decision feedback equalizer, wherein the clock and data recovery circuit is configured to generate an extracted clock signal from at least a portion of the equalized data signals based on a delay adjust signal; and
an adaptation circuit coupled to the continuous time filter, the decision feedback equalizer, and the clock and data recovery circuit, the adaptation circuit being configured to adapt equalization according to at least one dithering algorithm by adjusting the delay adjust signal based on a mean square error of the equalized data signals,
wherein the adaptation circuit is configured to adapt the equalization according to the at least one dithering algorithm by adjusting the delay adjust signal in a same direction as a previous adjustment to the equalization if a mean square error of the equalized data signals decreases and adjusting the delay adjust signal in an opposite direction from the previous adjustment to the equalization if the mean square error of the equalized data signals increases.
17. The apparatus of claim 16 , further comprising a continuous time filter configured to provide a filtered signal to the decision feedback equalizer.