Optical receiver having fractional sampling

1. An optical receiver for receiving an incoming optical signal carrying symbols, the optical receiver comprising:

an analog-to-digital converter (ADC) operating at a fractional sampling clock rate to convert an analog signal carrying the symbols to digital ADC output samples;

an interpolator to interpolate at an interpolation clock rate different than the fractional sampling clock rate between digital values derived from the digital ADC output samples to provide moving interpolations; and

an interpolation feedback loop to synchronize the moving interpolations with the symbols, the interpolation feedback loop comprising

a seed generator to compute seeds based in part on a ratio between the fractional sampling clock rate and the interpolation clock rate,

an accumulator to provide interpolation fractions at the interpolation clock rate, the accumulator being configured to

increment by the seeds to compute the interpolation fractions, and

generate an overflow when an increment by a current one of the seeds causes a modulus of the accumulator to be exceeded,

wherein the interpolator is configured to

use the interpolation fractions to interpolate between the digital values to compute values of the moving interpolations,

operate with the interpolation clock rate to respond to the overflow by reading a new one of the digital values, and

use a current one of the interpolation fractions to interpolate between the new digital value and a previous one of the digital values when the accumulator generates the overflow or to interpolate by the current interpolation fraction between a previous one of the digital values and a second previous one of the digital values when the accumulator does not generate the overflow.

2. The optical receiver of claim 1 , wherein the fractional sampling clock rate is configured to provide fewer than two of the digital ADC output samples for one of the symbols.

3. The optical receiver of claim 1 , wherein

the interpolation clock rate is configured to operate at greater than two times an expected rate of the symbols, and

the feedback interpolation loop is configured to synchronize the moving interpolations to two of the moving interpolations for one of the symbols.

4. The optical receiver of claim 1 , wherein

the interpolator is configured as a first polarization state interpolator to interpolate between the digital values corresponding to a first polarization of the optical signal to compute the moving interpolations for the first polarization, and

the optical receiver further comprises:

a second polarization interpolator configured to use the same interpolation fractions to interpolate between digital values corresponding to a second polarization of the optical signal to compute the moving interpolations for the second polarization; and

a data estimator to use the first and the second polarization moving interpolations to estimate data carried by the optical signal.

5. The optical receiver of claim 1 , wherein the seed generator is configured to compute the seeds based in part on an overrate compensation to compensate for an expected offset between the interpolation clock rate and a selected multiple of a rate of the symbols.

6. The optical receiver of claim 1 , wherein

the interpolation feedback loop includes

a timing error detector to determine timing errors between the moving interpolations and the symbols, and

the seed generator is configured to use the timing errors for computing the seeds.

7. The optical receiver of claim 1 , wherein

the interpolation feedback loop includes

the interpolator to provide first moving interpolations to a data estimator,

a second stage interpolator to interpolate between the moving interpolations to provide second moving interpolations at a rate different than the first moving interpolations,

a timing error detector to determine timing errors between the second interpolations and the symbols, and

the seed generator to use the timing errors to generate the seeds to synchronize the moving interpolations to a rate different than the second interpolations.

8. The optical receiver of claim 1 , further including:

a FIFO to provide the digital values to the interpolator; and

a clocking inhibitor to detect validity of the FIFO and to prevent the interpolator from providing the moving interpolations when the FIFO is not valid.

9. The optical receiver of claim 1 , wherein

the fractional sampling clock rate is operated at a free running rate not synchronized to the symbols to provide the digital ADC output samples, and

the interpolation feedback loop is configured to provide the moving interpolations synchronized to two of the moving interpolations for one of the symbols.

10. A method for receiving an incoming optical signal carrying symbols, the method comprising:

converting an analog signal carrying the symbols to digital ADC output samples at a fractional sampling clock rate;

interpolating at an interpolation clock rate different than the fractional sampling clock rate between digital values derived from the digital ADC output samples to provide moving interpolations; and

synchronizing the moving interpolations with the symbols using feedback from the moving interpolations, said synchronizing comprising

generating seeds based in part on a ratio between the fractional sampling clock rate and the interpolation clock rate, and

providing interpolation fractions at the interpolation clock rate at least in part by

incrementing accumulations by the seeds for computing the interpolation fractions, and

generating an accumulation overflow when an increment by a current one of the seeds causes an accumulation modulus to be exceeded,

wherein said interpolating includes

using the interpolation fractions for interpolating between the digital values to compute values of the moving interpolations,

operating at the interpolation clock rate to respond to the overflow by reading a new one of the digital values,

interpolating with a current one of the interpolation fractions between the new digital value and a previous one of the digital signal values when the overflow is generated, and

interpolating with the current interpolation fraction between a previous one of the digital values and a second previous one of the digital values when the overflow is not generated.

11. The method of claim 10 , wherein said converting the analog signal at the fraction sampling clock rate includes

issuing fewer than two of the digital ADC output samples for one of the symbols.

12. The method of claim 10 , wherein said synchronizing includes

operating with an interpolation clock rate greater than two times an expected rate of the symbols, and

synchronizing the moving interpolations with the feedback to two of the moving interpolations for one of the symbols.

13. The method of claim 10 , wherein

said interpolating at the interpolation clock rate includes

interpolating between the digital values corresponding to a first polarization of the optical signal to compute the moving interpolations for the first polarization, and

the method further comprises:

interpolating between digital values corresponding to a second polarization of the optical signal to compute the moving interpolations for the second polarization using the same the interpolation fractions; and

using the first and second polarization moving interpolations for estimating data carried by the optical signal.

14. The method of claim 10 , wherein said generating the seeds includes

biasing the seeds with an overrate compensation to mitigate an expected offset between the interpolation clock rate and a selected multiple of a rate of the symbols.

15. The method of claim 10 , wherein:

synchronizing includes determining timing errors between the moving interpolations and the symbols; and using the timing errors for generating the seeds.

16. The method of claim 10 , wherein said synchronizing further includes

interpolating between the moving interpolations to provide second interpolations,

determining the timing errors between the second interpolations and the symbols, and

using the timing errors to generate the seeds for synchronizing the moving interpolations to a rate different than the second interpolations.

17. The method of claim 10 , further comprising:

providing the digital values from a FIFO; and

preventing the interpolating when the FIFO is determined to be not valid.

18. The method of claim 10 , further comprising:

operating the fractional sampling clock rate at a free running rate not synchronized to the symbols to provide the digital ADC output samples; and

synchronizing the moving interpolations to two of the moving interpolations to one of the symbols.