Multi-channel digital pulse width modulator (DPWM)
View Patent ↗A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers.
1. A multiple channel Digital Pulse Width Modulator (DPWM) comprising:
a single delay locked loop with a delay line, the delay line producing a number of outputs;
circuitry connected to at least some of the outputs of the of the delay line to use a delay line mask to mask a portion of the delay line outputs to produce modified outputs so as to prevent premature pulse width reset; and
multiple pulse width modulators receiving the modified outputs from the circuitry, the multiple pulse width modulators producing pulse width modulated signals.
2. The multiple channel DPWM of claim 1 , wherein the circuitry uses AND elements to AND the portion of the delay line outputs with the delay line mask.
3. The multiple channel DPWM of claim 1 , wherein the portion of the delay outputs are consecutive higher outputs of the delay line.
4. The multiple channel DPWM of claim 1 , wherein the delay line mask goes low right before a first output of the delay line goes high.
5. The multiple channel DPWM of claim 1 , wherein the circuitry includes a sliding window delay.
6. The multiple channel DPWM of claim 5 , wherein the sliding window delay is implemented by ANDing outputs of the delay line.
7. The multiple channel DPWM of claim 5 , wherein the sliding window delay compensates for a greater than 50% duty cycle clock signal in the delay line.
8. The multiple channel DPWM of claim 1 , wherein the circuitry includes ANDs wherein some of the ANDs have two delay line outputs as inputs and other ANDs have two delay line outputs and the delay line mask as inputs.
9. The multiple channel DPWM of claim 1 , wherein the pulse width modulators include jitter tolerance look ahead circuits to prevent jitter from causing premature reset of a pulse width modulated signal.
10. The multiple channel DPWM of claim 9 , wherein the jitter tolerance look ahead circuits include circuitry that tests whether a selected multiplexer address is above a certain value, if so, the jitter tolerance look ahead circuit prevents any reset until a certain delay line output changes.
11. The multiple channel DPWM of claim 10 , wherein the jitter tolerance look ahead circuits use a delay line mask.
12. The multiple channel DPWM of claim 1 , wherein the pulse width modulators include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers.
13. A multiple channel Digital Pulse Width Modulator (DPWM) comprising:
a single delay locked loop with a delay line; and
multiple pulse width modulators operably connected to the delay locked loop, the multiple pulse width modulators producing pulse width modulated signals, wherein the pulse width modulators include jitter tolerance look ahead circuits to prevent jitter from causing premature reset of a pulse width modulated signal.
14. The multiple channel DPWM of claim 13 , wherein the jitter tolerance look ahead circuits include circuitry that tests whether a selected multiplexer address is above a certain value, if so, the jitter tolerance look ahead circuit prevents any reset until a certain delay line output changes.
15. The multiple channel DPWM of claim 14 , wherein the certain delay line output change is the change of a specific modified delay line output.
16. The multiple channel DPWM of claim 13 , wherein the jitter tolerance look ahead circuits use a delay line mask.
17. The multiple channel DPWM of claim 13 , further comprising circuitry connected to at least some outputs of the of the delay line to use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset, the modified outputs being provided to the multiple pulse width modulators.
18. The multiple channel DPWM of claim 17 , wherein the circuitry includes ANDs wherein some of the ANDs have two delay line outputs as inputs and other ANDs have two delay line outputs and the delay line mask as inputs.
19. The multiple channel DPWM of claim 17 , wherein at least one of the multiple modified outputs are provided to the jitter tolerance look ahead circuit.
20. The multiple channel DPWM of claim 13 , wherein the pulse width modulators include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers.
21. A multiple channel Digital Pulse Width Modulator (DPWM) comprising:
a single delay locked loop with a delay line, the delay line producing a number of outputs;
circuitry connected to at least some of the outputs of the of the delay line to produce modified outputs, the modified outputs compensating for a greater than 50% duty cycle clock signal in the delay line; and
multiple pulse width modulators receiving the modified outputs from the circuitry, the multiple pulse width modulators producing pulse width modulated signals.
22. The multiple channel DPWM of claim 21 , wherein the circuitry compensation comprises a sliding window delay.
23. The multiple channel DPWM of claim 22 , wherein the sliding window delay is implemented by ANDing outputs of the delay line.
24. The multiple channel DPWM of claim 21 , wherein the circuitry includes ANDs wherein some of the ANDs have two delay line outputs as inputs and other ANDs have two delay line outputs and a delay line mask as inputs.
25. A multiple channel Digital Pulse Width Modulator (DPWM) comprising:
a single delay locked loop with a delay line; and
multiple pulse width modulators operably connected to the delay locked loop, the multiple pulse width modulators producing pulse width modulated signals, wherein the pulse width modulators include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers.