Thin film transistor array panel used for liquid crystal display and a manufacturing method thereof
View Patent ↗A method for manufacturing a TFT array panel is presented. The method includes: forming a gate line and a gate electrode on a substrate with a first mask; depositing an insulation layer on the gate line and on the gate electrode; depositing a semiconductor layer; depositing an n+ amorphous silicon layer; forming a data line, a source electrode and a drain electrode on the substrate with a second mask; removing the exposed portion of the n+ amorphous silicon layer; forming a passivation film on the semiconductor layer, the n+ amorphous silicon layer, the data line, the source electrode and the drain electrode by using a third mask such that a portion of the drain electrode and the semiconductor layer is exposed; removing the exposed portion of the semiconductor layer; and forming a pixel electrode connected to the exposed portion of the drain electrode by using a fourth mask.
1. A method for manufacturing a thin film transistor array panel, the method comprising:
forming a gate line and a gate electrode on a substrate by using a first mask;
depositing an insulation layer on the gate line and on the gate electrode;
depositing a semiconductor layer on the insulating layer;
depositing an n+ amorphous silicon layer on the semiconductor layer;
forming a data line, a source electrode and a drain electrode on the substrate by using a second mask before first etching of the n+ amorphous silicon layer;
removing the exposed portion of the n+ amorphous silicon layer;
forming a passivation film on the semiconductor layer, the n+ amorphous silicon layer, the data line, the source electrode and the drain electrode by using a third mask, the passivation film exposing a portion of the drain electrode and a portion of the semiconductor layer;
removing the exposed portion of the semiconductor layer by using the passivation film as a mask; and
forming a pixel electrode connected to the exposed portion of the drain electrode by using a fourth mask.
2. The method of claim 1 , wherein the passivation film is formed of an opaque material.
3. A method for manufacturing a thin film transistor array panel, the method comprising:
forming a gate line and a gate electrode on a substrate by using a first mask;
depositing an insulation layer on the gate line and on the gate electrode;
depositing a semiconductor layer on the insulating layer;
depositing an n+ amorphous silicon layer on the semiconductor layer;
forming a data line, a source electrode and a drain electrode on the substrate by using a second mask before first etching of the n+ amorphous silicon layer;
removing the exposed portion of the n+ amorphous silicon layer;
forming a passivation film on the semiconductor layer, the n+ amorphous silicon layer, the data line, the source electrode and the drain electrode by using a third mask, the passivation film exposing a portion of the drain electrode and a portion of the semiconductor layer;
removing the exposed portion of the semiconductor layer and the insulation layer, wherein the semiconductor layer is removed by using the passivation film as a mask; and
forming a pixel electrode connected to the exposed portion of the drain electrode by using a fourth mask,
wherein the passivation film overlaps portions of the gate line and the gate electrode.
4. The method of claim 3 , wherein the passivation film is formed of an opaque material.