IP Library › Granted Patent US 8,225,245

Granted Patent B2

US 8,225,245 · App. 12/609,370 · Granted Jul 17, 2012

Method of implementing physically realizable and power-efficient clock gating in microprocessor circuits

Assignee: Oracle America, Inc.

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 8,225,245
App. No.: 12/609,370
Granted: Jul 17, 2012
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions.

Claims (70)

1. A method of merging gated-clock domains in a semiconductor design comprising:

selecting, by a computer processor, a set of initial clock gating functions comprising a plurality of clock gating functions, wherein each clock gating function comprises a support set of variables;

defining, by the computer processor, a plurality of subsets of clock gating functions, each subset comprising a plurality of clock gating functions from the set of initial clock gating functions;

defining a set of super clock gating functions;

defining a set of final clock gating functions;

for each subset of clock gating functions:

producing a set of quantified functions by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset;

when the set of quantified function are equal, selecting any one of the quantified functions as a super clock gating function;

adding the super clock gating function to the set of super clock gating functions;

when the set of super clock gating function contains at least one super clock gating function:

sorting the set of super clock gating functions according to a criterion;

selecting the super clock gating function that best achieves the criterion;

adding the selected super clock gating function to the set of final clock gating functions;

removing the selected super clock gating function from the set of super gating functions;

modifying the remaining super clock gating functions from the set of super clock gating functions by preventing flip-flops gated by the selected super clock gating function from being gated by the remaining super clock gating functions; and

outputting a gate-level netlist that comprises the set of final clock gating functions.

2. The method of claim 1 , wherein each subset is comprised of a pair of clock gating functions.

3. The method of claim 1 , wherein the criterion is a number of gated flip-flops.

4. The method of claim 1 , wherein the criterion is a clock gating efficiency.

5. The method of claim 1 , wherein the criterion is a function support size.

6. A method of implementing merged gated-clock domains in a semiconductor design comprising:

outputting, by a computer processor, an initial gate-level netlist that comprises a plurality of gated-clock domains;

merging, by a computer processor, the gated-clock domains, wherein the merging comprises:

selecting a set of initial clock gating functions comprising a plurality of clock gating functions, wherein each clock gating function comprises a support set of variables;

defining a plurality of subsets of clock gating functions, each subset comprising a plurality of clock gating functions from the set of initial clock gating functions;

defining a set of super clock gating functions;

defining a set of final clock gating functions;

for each subset of clock gating functions:

when the set of quantified function are equal, selecting any one of the quantified functions as a super clock gating function;

adding the super clock gating function to the set of super clock gating functions;

when the set of super clock gating function contains at least one super clock gating function:

sorting the set of super clock gating functions according to a criterion;

selecting the super clock gating function that best achieves the criterion;

removing the selected super clock gating function from the set of super gating functions;

adding the selected super clock gating function to the set of final clock gating functions;

outputting a merged gate-level netlist that comprises the set of final clock gating functions;

back-annotating the merged gate-level netlist;

outputting a final gate-level netlist; and

inputting the final gate-level netlist into a physical layout generation phase.

7. The method of claim 6 , wherein each subset is comprised of a pair of clock gating functions.

8. The method of claim 6 , wherein the criterion is a number of gated flip-flops.

9. The method of claim 6 , wherein the criterion is a clock gating efficiency.

10. The method of claim 6 , wherein the criterion is a function support size.

11. A system for designing a semiconductor with merged gated-clock domains comprising:

a microprocessor;

an input device;

an output device; and

a storage device,

wherein the microprocessor executes instructions that perform the following: