Electrostatic discharge protection

1. An integrated circuit comprising a driver element electrically connected to a pin of a package housing the integrated circuit, the driver element being associated with a detection element such that on detection of an electrostatic discharge event occurring at the pin by the detection element a system associated with the integrated circuit can be activated, wherein a voltage of a substrate on which the driver element is mounted increases when an electrostatic discharge event occurs at the pin, and wherein the detection element is located in close proximity to the driver element such that when an electrostatic discharge event occurs at the pin the detection element is activated by the increased voltage of the substrate.

2. An integrated circuit according to claim 1 wherein the driver element is tolerant of electrostatic discharge events.

3. An integrated circuit according claim 1 wherein the system associated with the integrated circuit comprises an electrostatic discharge protection system.

4. An integrated circuit according to claim 3 wherein the electrostatic discharge protection system comprises a transistor which is configured to connect a power supply rail of the integrated circuit to ground for a predetermined time period in the event of an electrostatic discharge event occurring at the pin.

5. An integrated circuit according to claim 4 wherein the electrostatic discharge protection system further comprises a capacitor for setting the predetermined period of time.

6. An integrated circuit according to claim 5 wherein the detection element is configured to discharge the capacitor in the event of an electrostatic discharge event occurring at the pin.

7. An integrated circuit according to claim 3 wherein the electrostatic discharge protection system comprises a transistor which is configured to disconnect part of the integrated circuit from a power supply rail of the integrated circuit in the event of an electrostatic discharge event occurring at the pin.

8. An integrated circuit according to claim 3 further comprising a resistive element for limiting current to the electrostatic discharge protection system.

9. An integrated circuit according to claim 1 wherein the system associated with the integrated circuit comprises a correction system for a circuit.

10. An integrated circuit according to claim 9 wherein the correction system comprises a processor which is part of a digital circuit, the processor being configured to take corrective action when an electrostatic discharge event is detected by the detection element of the integrated circuit.

11. An integrated circuit according to claim 10 wherein the correction system comprises a software program running on the processor, the software program being configured to cause the processor to take corrective action when an electrostatic discharge event is detected by the detection element of the integrated circuit.

12. An integrated circuit according to claim 9 wherein the correction system comprises a digital circuit which is configured to take corrective action when an electrostatic discharge event is detected by the detection element of the integrated circuit.

13. An integrated circuit according to claim 9 wherein the correction system comprises a reset mechanism for resetting the circuit to a known correct state of operation.

14. An integrated circuit according to claim 1 wherein the detection element comprises a transistor.

15. An integrated circuit according to claim 1 wherein the driver element comprises a p-channel MOSFET.

16. An integrated circuit according to claim 1 wherein the detection element comprises an n-channel MOSFET.

17. An integrated circuit according to claim 1 wherein the driver element comprises an n-channel MOSFET.

18. An integrated circuit according claim 1 wherein a plurality of detection elements are provided.

19. A device comprising an integrated circuit according to claim 1 .

20. An integrated circuit comprising a driver element electrically connected to a pin of a package housing the integrated circuit, the driver element being associated with a detection element such that on detection of an electrostatic discharge event occurring at the pin by the detection element a system associated with the integrated circuit can be activated, wherein the detection element is substantially surrounded by the driver element.

21. A method of reacting to an electrostatic discharge event occurring at a pin of a package of an integrated circuit, the method comprising detecting, at a detection element, the occurrence of the electrostatic discharge event and causing activation of a system associated with the integrated circuit, wherein a voltage of a substrate on which a driver element of the integrated circuit is mounted increases when an electrostatic discharge event occurs at the pin, and wherein the detection element is substantially surrounded by the driver element.

22. A method according to claim 21 wherein the driver element comprises a p-channel MOSFET.

23. A method according to claim 21 wherein the detection element comprises an n-channel MOSFET.

24. A method according to claim 21 wherein the driver element comprises an n-channel MOSFET.

25. A method according to claim 21 wherein a plurality of detection elements are provided in the integrated circuit.

26. A method according to claim 21 wherein detecting the occurrence of an electrostatic discharge event comprises detecting the increased voltage of the substrate.

27. A method according to claim 21 wherein the driver element is tolerant of electrostatic discharge events.

28. A method according to claim 21 wherein the system associated with the integrated circuit comprises an electrostatic discharge protection system.

29. A method according to claim 28 wherein the electrostatic discharge protection system comprises a transistor which is configured to connect a power supply rail of the integrated circuit to ground for a predetermined time period in the event of an electrostatic discharge event occurring at the pin.

30. A method according to claim 29 wherein the electrostatic discharge protection system further comprises a capacitor for setting the predetermined period of time.

31. A method according to claim 30 wherein the detection element is configured to discharge the capacitor in the event of an electrostatic discharge event occurring at the pin.

32. A method according to claim 28 wherein the electrostatic discharge protection system comprises a transistor which is configured to disconnect part of the integrated circuit from a power supply rail of the integrated circuit in the event of an electrostatic discharge event occurring at the pin.

33. A method according to claim 32 wherein the electrostatic discharge protection system further comprises a resistive element for limiting current to the electrostatic discharge protection system.

34. A method according to claim 21 wherein the system associated with the integrated circuit comprises a correction system for a circuit.

35. A method according to claim 34 wherein the correction system comprises a processor which is part of a digital circuit, the processor being configured to take corrective action when an electrostatic discharge event is detected.

36. A method according to claim 35 wherein the correction system comprises a software program running on the processor, the software program being configured to cause the processor to take corrective action when an electrostatic discharge event is detected.

37. An integrated circuit according to claim 34 wherein the correction system comprises a digital circuit which is configured to take corrective action when an electrostatic discharge event is detected.

38. A method according to claim 34 wherein the correction system comprises a reset mechanism for resetting the circuit to a known correct state of operation.

39. A method according to claim 21 wherein the occurrence of an electrostatic discharge event is detected by a detection transistor.