Semiconductor package
View Patent ↗A semiconductor package includes a chip base material; a capacitor formed on the base material; and a cover formed over the base material to cover the capacitor, and having a side portion and an upper portion. The base material is provided with a bonding pattern connecting the base material and the cover to cover the capacitor. The bonding pattern includes a region A having a substantially uniform pattern width A, and at least one region B having a pattern width B which is larger than the width pattern width A.
1. A semiconductor package comprising:
a base material;
a capacitor formed on the base material; and
a cover formed over the base material to cover the capacitor, and having a side portion and an upper portion, wherein
the base material is provided with a bonding pattern connecting the base material and the cover to cover the capacitor, and
the bonding pattern, which connects the base material and the cover, includes a region A having a substantially uniform pattern width A, and at least one region B having a pattern width B which is larger than the width pattern width A.
2. The semiconductor package of claim 1 , wherein the region B occupies from 10% to 30% of the bonding pattern of the cover.
3. The semiconductor package of claim 1 , wherein the bonding pattern is made of metal.
4. The semiconductor package of claim 1 , wherein the bonding pattern is formed on the base material by resist patterning.
5. The semiconductor package of claim 1 , wherein a part of the region B is formed inside the side portion of the cover.
6. The semiconductor package of claim 1 , wherein
a part of the region A is formed inside the side portion of the cover,
a part of the region B is formed inside the side portion of the cover, and
the part of the region B is formed inner than the part of the region A.
7. The semiconductor package of claim 1 , wherein multiple ones of the at least one region B are formed in two portions.
8. The semiconductor package of claim 7 , wherein the regions B formed in two portions are positioned point-symmetrically with respect to the base material.
9. The semiconductor package of claim 1 , wherein the region B is positioned inside and adjacent to the bonding pattern of the base material.
10. The semiconductor package of claim 1 , wherein the pattern width B is from 1.2 to 2 times as large as the pattern width A.
11. The semiconductor package of claim 1 , wherein the capacitor is a semiconductor device.
12. The semiconductor package of claim 1 , wherein the capacitor is a MEMS microphone.
13. The semiconductor package of claim 1 , wherein a through-hole is formed in either one of the base material and the cover.
14. The semiconductor package of claim 1 , wherein a surface of the cover which is in contact with the bonding pattern is formed to be parallel to a surface of the bonding pattern which is in contact with the cover.
15. The semiconductor package of claim 1 , wherein the side portion of the cover bends toward the outside of the base material near the bonding portion of the base material and the cover.
16. The semiconductor package of claim 1 , wherein
the side portion of the cover is constituted by a portion C which is near the bonding portion of the base material and the cover, and a portion D other than the portion C, and
the portion C has a smaller width than the portion D.
17. The semiconductor package of claim 1 , wherein
the side portion of the cover is constituted by a portion E which is near the bonding portion of the base material and the cover, and a portion F other than the portion E, and
a width of the portion E decreases gradually toward the bonding portion compared to the portion F.
18. The semiconductor package of claim 1 , wherein the cover is bonded to the base material using a conductive bonding material.