Thin film transistor array panel and method for manufacturing the same

1. A thin film transistor array panel, comprising:

a substrate comprising a display area and a peripheral area;

a thin film transistor disposed in the display area;

a gate line disposed in the display area and connected to the thin film transistor;

a data line disposed in the display area and connected to the thin film transistor;

a pixel electrode disposed in the display area and connected to the thin film transistor;

a first repair line disposed in the peripheral area and being configured to repair when at least one of the gate line and the data line is disconnected; and

a first detour line disposed in the peripheral area and comprising at least one first resistor having a higher resistance than a remaining portion of the first detour line, wherein the first detour line comprises two ends and both ends of the first detour line are connected to the first repair line.

2. The thin film transistor array panel of claim 1 , further comprising:

a first diode connected between the first detour line and the first repair line.

3. The thin film transistor array panel of claim 2 , wherein

the first resistor comprises two resistors that are coupled in series, and

one terminal of the first diode is connected to the first detour line at a portion of the first detour line between the two resistors.

4. The thin film transistor array panel of claim 3 , wherein a plurality of first diodes are connected between the first detour line and the first repair line.

5. The thin film transistor array panel of claim 4 , further comprising:

a second detour line disposed in the peripheral area and coupled in parallel with the first detour line, wherein the second detour line comprises two ends and both ends of the second detour line are connected to the first repair line.

6. The thin film transistor array panel of claim 5 , further comprising:

a second repair line disposed in the peripheral area and parallel to the first repair line;

a third detour line disposed in the peripheral area and comprising at least one second resistor having a higher resistance than the remaining portion of the third detour line, wherein the third detour line comprises two ends and both ends of the third detour line are connected to the second repair line; and

a second diode connected between the third detour line and the second repair line.

7. The thin film transistor array panel of claim 6 , wherein

the second resistor comprises two resistors that are coupled in series, and

one terminal of the second diode is connected to the third detour line at a portion of the third detour line between the two resistors.

8. The thin film transistor array panel of claim 7 , wherein a plurality of second diodes are connected between the third detour line and the second repair line.

9. The thin film transistor array panel of claim 8 , further comprising:

a fourth detour line disposed in the peripheral area and coupled with the third detour line in parallel, wherein the fourth detour line comprises two ends and both ends of the fourth detour line are connected to the second repair line.

10. The thin film transistor array panel of claim 9 , wherein

the first detour line comprises a first portion disposed with the same layer as the gate line and a second portion disposed with the same layer as the data line, and the first resistor comprises a connection disposed with the same layer as the pixel electrode and connecting between the first portion and the second portion, and

the third detour line comprises a third portion disposed with the same layer as the gate line and a fourth portion disposed with the same layer as the data line, and the second resistor comprises a connection disposed with the same layer as the pixel electrode and connecting between the third portion and the fourth portion.

11. The thin film transistor array panel of claim 10 , wherein

the first diode and the second diode each further comprise:

a control electrode disposed with the same layer as the gate line;

a semiconductor disposed on the control electrode, and insulated from the control electrode;

an input electrode disposed with the same layer as the pixel electrode and connected to the control electrode and the semiconductor; and

an output electrode disposed with the same layer as the data line and connected to the semiconductor.

12. A thin film transistor array panel comprising:

a substrate comprising a display area and a peripheral area;

a thin film transistor disposed in the display area;

a gate line disposed in the display area and connected to the thin film transistor;

a data line disposed in the display area and connected to the thin film transistor;

a pixel electrode disposed in the display area and connected to the thin film transistor;

a first repair line disposed in the peripheral area and being configured to repair when at least one of the gate line and the data line is disconnected; and

a first detour line disposed in the peripheral area, wherein the first detour line comprises two ends and both ends of the first detour line are connected to the first repair line, and

wherein a first diode is connected between the first detour line and the first repair line.

13. The thin film transistor array panel of claim 12 , further comprising:

a second detour line disposed in the peripheral area and coupled with the first detour line in parallel, wherein the second detour line comprises two ends and both ends of the second detour line are connected to the first repair line.

14. The thin film transistor array panel of claim 13 , further comprising:

a second repair line disposed in the peripheral area and parallel to the first repair line;

a third detour line disposed in the peripheral area, wherein the third detour line comprises two ends and both ends of the third detour line are connected to the second repair line; and

a second diode connected between the third detour line and the second repair line.