Protecting external volatile memories using low latency encryption/decryption

1. A method, implemented in one or more data processing devices, of encrypting data for temporary storage in a volatile memory operably connected to a memory encryption unit of a device adapted for processing the data, the method comprising:

generating one or more keys within the device;

receiving, at the memory encryption unit, an N-bit block of data to be stored temporarily in an encrypted form in the volatile memory, wherein N is 8 or more;

dividing the N-bit block of data into two more sub-blocks of data, wherein each sub-block contains fewer than N-bits:

encrypting each sub-block of data with the memory encryption unit using one or more of the generated keys;

combining the encrypted sub-blocks into an N-bit block of encrypted data independent of the one or more keys; and

temporarily storing the encrypted block of data in the volatile memory.

2. The method of claim 1 , wherein generating the one or more keys within the device includes generating the one or more keys upon booting the device.

3. The method of claim 1 , wherein generating the one or more keys within the device includes generating the one or more keys based on a memory address to which the block of data is written.

4. The method of claim 1 , wherein the N-bit block of data is a 64-bit block of data.

5. The method of claim 1 , wherein each sub-block contains M-bits and M is equal to N/4, N/8, N/16, N/32, or N/64.

6. The method of claim 1 , wherein each sub-block contains 8-bits.

7. The method of claim 1 , wherein encrypting each sub-block includes applying a non-linear transformation to data bits of the sub-block.

8. The method of claim 7 , wherein the non-linear transformation includes applying an S-block transformation of the data bits of the sub-block.

9. The method of claim 1 , wherein encrypting each sub-block includes applying N rounds of a symmetric block cipher function to the sub-block, where N is greater than 2.

10. The method of claim 9 , wherein different subkey is used in each round.

11. A data processing apparatus, the apparatus comprising:

a volatile memory;

a random number generator adapted for generating random numbers from which one or more keys are generated;

a memory encryption unit configured for:

receiving an N-bit block of data to be stored temporarily in an encrypted form in the volatile memory, wherein N is 8 or more;

dividing the N-bit block of data into two more sub-blocks of data, wherein each sub-block contains fewer than N-bits;

encrypting each sub-block of data using the one or more keys;

combining the encrypted sub-blocks into an N-bit block of encrypted data independent of the one or more keys; and

writing the encrypted N-bit block of data to the volatile memory.

12. The data processing apparatus of claim 11 , wherein the memory encryption unit is further configured for:

receiving an the encrypted N-bit block of data from the volatile memory, wherein N is 8 or more;

dividing the encrypted N-bit block of data into two more sub-blocks of data, wherein each sub-block contains fewer than N-bits;

decrypting each sub-block of data using the one more keys;

combining the decrypted sub-blocks into an N-bit block of unencrypted data; and

passing the block of unencrypted data to a processing device.

13. The data processing apparatus of claim 11 , wherein generating the one or more keys within the device includes generating the one or more keys upon booting the device.

14. The data processing apparatus of claim 11 , wherein the memory encryption unit is further configured for encrypting each sub-block of data using keys based on a memory address to which the N-bit block of data is to be written.

15. The data processing apparatus of claim 11 , wherein the N-bit block of data is a 64-bit block of data.

16. The data processing apparatus of claim 11 , wherein each sub-block contains M-bits and M is equal to N/4, N/8, N/16, N/32 or N/64.

17. The data processing apparatus of claim 11 , wherein each sub-block contains 8-bits.

18. The data processing apparatus of claim 11 , wherein encrypting each sub-block includes applying a non-linear transformation to data bits of the sub-block.

19. The data processing apparatus of claim 18 , wherein the non-linear transformation includes applying an S-block transformation of the data bits of the sub-block.

20. The data processing apparatus of claim 11 , wherein encrypting each sub-block includes applying N rounds of a symmetric block cipher function to the sub-block, where N is greater than 2.

21. The data processing apparatus of claim 20 , wherein a different subkey is used in each round.

22. A data processing apparatus for processing protected content, the apparatus comprising:

a central processing unit;

a volatile memory;

a random number generator adapted for generating random numbers from which one or more keys are generated;

a memory encryption unit operably connected to the volatile memory and configured for:

receiving an N-bit block of data to be stored temporarily in an encrypted form in the volatile memory from the central processing unit, wherein N is 8 or more;

dividing the N-bit block of data into two more first sub-blocks of data, wherein each first sub-block contains eight or fewer bits;

encrypting each first sub-block of data using a non-linear symmetric algorithm based on the one more keys;

combining the encrypted first sub-blocks into an N-bit block of encrypted data independent of the one or more keys;

writing the encrypted N-bit block of data to the volatile memory;

receiving the encrypted N-bit block of data from the volatile memory;

dividing the encrypted N-bit block of data into two more second sub-blocks of data, wherein each second sub-block contains eight or fewer bits;

decrypting each second sub-block of data using the non-linear symmetric algorithm based on the one more keys;

combining the decrypted second sub-blocks into an N-bit block of decrypted data; and

transmitting the decrypted N-bit block of data to a rendering device.