Read circuit for semiconductor memory device and semiconductor memory device
View Patent ↗Provided is a read circuit for a semiconductor memory device which may have a reduced circuit scale, and a semiconductor memory device. In a plurality of sense amplifiers of the read circuit of the semiconductor memory device, for serially reading data from a serial output terminal, if a number of byte selectors which may be selected to determine an address at a predetermined time before determination of the address is four, only four sense amplifiers are required in total, and hence the read circuit and the semiconductor memory device are reduced in circuit scale.
1. A read circuit for a semiconductor memory device, for serially reading data from a serial output terminal, comprising:
a plurality of byte selectors each for outputting first to eighth data signals from a plurality of predetermined memory cells based on an address;
a plurality of sense amplifiers for simultaneously sensing the first data signals from the plurality of byte selectors which are selected to determine the address before the address is determined, and sensing the second to eighth data signals from one of the plurality of byte selectors which corresponds to a determined address when the address is determined; and
a selector circuit for selectively reading one of the first data signals which is sensed by the one of the plurality of byte selectors which corresponds to the determined address after the address is determined, and sequentially selectively reading the second to eighth data signals from the one of the plurality of byte selectors;
wherein the plurality of sense amplifiers simultaneously sense the first data signals from the plurality of byte selectors which are selected to determine the address before the address is determined, simultaneously sense second to fourth data signals from the one of the plurality of byte selectors which corresponds to the determined address, simultaneously sense fifth and sixth data signals from the one of the plurality of byte selectors which corresponds to the determined address, and simultaneously sense seventh and eighth data signals from the one of the plurality of byte selectors which corresponds to the determined address.
2. A read circuit for a semiconductor memory device according to claim 1 , wherein, before the address is determined, an address signal except for low-order two bits of a plurality of bits necessary to determine the address is input.
3. A read circuit for a semiconductor memory device according to claim 2 , wherein the four sense amplifiers are provided.
4. A read circuit for a semiconductor memory device according to claim 1 , further comprising a plurality of latches for latching signals from the plurality of sense amplifiers.
5. A read circuit for a semiconductor memory device according to claim 1 , further comprising a switch circuit provided between the plurality of byte selectors and the plurality of sense amplifiers.
6. A read circuit for a semiconductor memory device according to claim 1 , wherein the semiconductor memory device is electrically rewritable.
7. A semiconductor memory device, comprising:
a row decoder;
a column decoder;
a memory array including a plurality of memory cells arranged in rows and an output bit line, at least one of the plurality of memory cells which is located in a predetermined row being selected by the row decoder and the column decoder;
a control circuit including an output signal line, for capturing an instruction and address data which are included in an input signal and making an access to at least one of the plurality of memory cells which is located in a row corresponding to the address data through the row decoder and the column decoder; and
a read circuit connected to the output bit line of the memory array and the output signal line of the control circuit, for serially outputting data from the at least one of the plurality of memory cells which is located in the row corresponding to the address data,
wherein the read circuit comprises:
a plurality of byte selectors connected to the output bit line, for outputting data from at least two of the memory cells which are located in rows which correspond to determined address data before the address data is determined;
a plurality of sense amplifiers connected to the plurality of byte selectors on a one-to-one basis;
a plurality of switch circuits provided between the plurality of byte selectors and the plurality of sense amplifiers; and
a selector circuit connected to the plurality of sense amplifiers, for switching and outputting outputs from the plurality of sense amplifiers after the address data is determined,
wherein after the address data is determined, a first data signal from one of the plurality of byte selectors which corresponds to the determined address data is selectively read by a first switch circuit of the plurality of switch circuits, and then second and subsequent data signals are sequentially selectively read by the plurality of switch circuits;
wherein the plurality of sense amplifiers simultaneously sense first data signals from the plurality of byte selectors which are selected to determine the address before the address is determined, simultaneously sense second to fourth data signals from the one of the plurality of byte selectors which corresponds to the determined address, simultaneously sense fifth and sixth data signals from the one of the plurality of byte selectors which corresponds to the determined address, and simultaneously sense seventh and eighth data signals from the one of the plurality of byte selectors which corresponds to the determined address.