Gate-charge retaining switch
This invention provides a means and method for preventing unwanted semiconductor turn-on and turn-off, caused by a high rate of voltage change, without significantly affecting the desired ON and OFF transitions of the semiconductor. According to this invention, time is provided during either or both bistable ON and OFF semiconductor states, during which the semiconductor gate is allowed to float, neither being driven ON or OFF, and circuitry for lowering gate-node impedance at non-transitional times to prevent state disruptions by dV/dT is provided.
1. A substantially bistable gate-charge-retaining power-switch comprising;
at least one gate-charge-retaining power transistor; and
control circuitry responsive to at least one control signal,
said control circuitry capable of injecting charge into and removing charge from the gate of the power transistor responsive to the control signal, and
circuitry responsive to at least one timing signal capable of modulating the impedance at the gate node of the power transistor to prevent disturbances of a bistable state by fast voltage changes,
wherein the power switch is bistable.
2. The switch of claim 1 wherein gate node impedance is modulated by application of plural ON signals per OFF signal.
3. The switch of claim 1 wherein gate node impedance is modulated by application of plural OFF signals per ON signal.
4. The switch of claim 1 wherein gate node impedance is modulated by generation of a high-impedence driver-dead state between ON signals and OFF signals.
5. The switch of claim 1 wherein plural power transistors are arranged in totem-pole configuration.