IP Library Granted Patent US 8,618,783
Granted Patent B2
US 8,618,783 · App. 12/617,427 · Granted Dec 31, 2013

DC-DC converter with adaptive phase compensation controller

Inventor: Hideta Oki (Kasugai, JP)
Assignee: Spansion LLC
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Quick Facts
Patent No.
US 8,618,783
App. No.
12/617,427
Granted
Dec 31, 2013
Kind
B2
Abstract

A DC-DC converter for generating an output voltage from input voltage, includes: an output stage for outputting the output voltage; an error amplifier having an input and a reference input for receiving a feedback voltage at the input in accordance with the output voltage and for receiving a reference voltage at the reference input, the error amplifier generating an amplified voltage for driving the output stage, the amplifier voltage corresponding to the difference between the feedback voltage and the reference voltage; a phase compensation unit for generating a phase compensation component to the feedback voltage; and a phase compensation controller for controlling the phase of the phase compensation unit; wherein the feedback voltage is determined by the output voltage plus said phase compensation component.

Claims (27)

1. A DC-DC converter for generating an output voltage from an input voltage, comprising:

an output stage to output the output voltage generated based on the input voltage;

an error amplifier having an input for receiving a feedback voltage in accordance with the output voltage, a first input for receiving a reference voltage and an output for generating an amplified voltage which drives the output stage, the amplified voltage corresponding to the difference between the feedback voltage and the reference voltage;

a phase compensation circuit to adjust a phase of the feedback voltage; and

a phase compensation controller to control a phase compensation component of the phase compensation circuit based on the input voltage and the output voltage,

wherein the phase compensation circuit includes a variable capacitor having a transistor whose backgate is coupled to a second input of the error amplifier,

wherein a capacitance of the variable capacitor is controlled based on a control voltage so as to become small when the control voltage becomes large and to become large when the control voltage becomes small,

wherein the control voltage is generated by amplifying a voltage difference between the input voltage and the output voltage.

2. The DC-DC converter of claim 1 , wherein the phase compensation circuit is a serial circuit including the variable capacitor and a resistor electrically connected between the input and the output, and wherein the phase compensation controller controls capacitance of the variable capacitor.

3. The DC-DC converter of claim 1 , wherein the phase compensation circuit is a serial circuit including the variable capacitor and a resistor electrically connected between the input and the output, and wherein the phase compensation controller controls capacitance of the variable capacitor.

4. The DC-DC converter of claim 2 , wherein the transistor is an N-channel floating MOS transistor including a gate of the N-channel MOS transistor receiving a control signal from the phase compensation controller.

5. The DC-DC converter of claim 3 , wherein the transistor is an N-channel floating MOS transistor including a gate of the N-channel MOS transistor receiving a control signal from the phase compensation controller.

6. The DC-DC converter of claim 1 , wherein the phase compensation circuit is a serial circuit including the variable capacitor and a variable resistor electrically connected between the input and the output, and wherein the phase compensation controller controls resistance of the variable resistor.

7. The DC-DC converter of claim 1 , wherein the phase compensation circuit is a serial circuit including the variable capacitor and a variable resistor electrically connected between the input and the output, and wherein the phase compensation controller controls resistance of the variable resistor.

8. The DC-DC converter of claim 6 , wherein the variable resistor is an N-channel MOS transistor, a gate of the N-channel MOS transistor receiving a control signal from the phase compensation controller, a drain of the N-channel MOS transistor electrically connecting to the output, a source of the N-channel MOS transistor electrically connecting to the input.

9. The DC-DC converter of claim 7 , wherein the variable resistor is an N-channel MOS transistor, a gate of the N-channel MOS transistor receiving a control signal from the phase compensation controller, a drain of the N-channel MOS transistor electrically connecting to the output, a source of the N-channel MOS transistor electrically connecting to the input.

10. The DC-DC converter of claim 1 , wherein the phase compensation circuit is a serial circuit including the variable capacitor and a variable resistor electrically connected between the input and the output, and wherein the phase compensation controller controls capacitance of the variable capacitor.

11. The DC-DC converter of claim 1 , wherein the phase compensation circuit is a serial circuit including the variable capacitor and a variable resistor electrically connected between the input and the output, and wherein the phase compensation controller controls and capacitance of the variable capacitor.

12. The DC-DC converter of claim 10 , wherein the variable capacitor is an N-channel MOS transistor, the gate of the N-channel MOS transistor receiving a control signal from the phase compensation controller, and wherein the variable resistor is an N-channel MOS transistor, the gate of the N-channel MOS transistor receiving the control signal from the phase compensation controller.

13. The DC-DC converter of claim 10 , wherein the variable capacitor is an N-channel MOS transistor, the gate of the N-channel MOS transistor receiving a control signal from the phase compensation controller, and wherein the variable resistor is an N-channel MOS transistor, the gate of the N-channel MOS transistor receiving the control signal from the phase compensation controller.

14. The DC-DC converter of claim 4 , wherein the phase compensation controller generates a difference voltage between the feedback voltage and the input voltage and wherein the phase compensation controller outputs the control signal in accordance with the difference voltage to the gate of the each N-channel MOS transistor.

15. The DC-DC converter of claim 5 , wherein the phase compensation controller generates a difference voltage between the feedback voltage and the input voltage and wherein the phase compensation controller outputs the control signal in accordance with the difference voltage to the gate of the each N-channel MOS transistor.

16. The DC-DC converter of claim 8 , wherein the phase compensation controller generates a difference voltage between the feedback voltage and the input voltage and wherein the phase compensation controller outputs the control signal in accordance with the difference voltage to the gate of the each N-channel MOS transistor.

17. The DC-DC converter of claim 9 , wherein the phase compensation controller generates a difference voltage between the feedback voltage and the input voltage and wherein the phase compensation controller outputs the control signal in accordance with the difference voltage to the gate of the each N-channel MOS transistor.

18. The DC-DC converter of claim 12 , wherein the phase compensation controller generates a difference voltage between the feedback voltage and the input voltage and wherein the phase compensation controller outputs the control signal in accordance with the difference voltage to the gate of the each N-channel MOS transistor.

19. The DC-DC converter of claim 13 , wherein the phase compensation controller generates a difference voltage between the feedback voltage and the input voltage and wherein the phase compensation controller outputs the control signal in accordance with the difference voltage to the gate of the each N-channel MOS transistor.

20. The DC-DC converter of claim 13 , wherein the phase compensation circuit includes a resistor coupled to a source and a drain of the transistor.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2017
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 043893/0186 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024748/0328 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2009
From: OKI, HIDETA
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 023530/0444 →
Priority Claims (1)
JP 2008-305307 · Nov 28, 2008 · national
Continuity (1)
Related Publication 20100134081A1 · Jun 3, 2010