Frequency compression for an interleaved power factor correction (PFC) converter

1. A controller for an interleaved power factor correction (PFC) converter that includes switches selectively turned ON and OFF to convert an input voltage to a desired output voltage, the controller comprising:

input terminals for monitoring an input voltage of the PFC converter, an output voltage of the PFC converter, a sum of inductor currents, and an amplified error signal that is based on the monitored output voltage;

a first circuit for generating an ON time current having a magnitude related to the amplified error signal and the monitored input voltage;

a second circuit for generating an OFF time current having a magnitude related to the ON time current, the monitored input voltage, and the monitored output voltage; and

gate drive circuitry that provides gate drive signals to the switches of the interleaved PFC converter at a frequency determined by magnitudes of the ON time current and the OFF time current.

2. The controller of claim 1 , wherein the magnitude of the ON time current is defined by the equation

I

ON

=

K

Vcomp

+

V

in

Rb

,

where I ON is the magnitude of the ON time current, K and Rb are constant values, Vcomp is the amplified error signal, and V in is the monitored input voltage.

3. The controller of claim 1 , wherein the magnitude of the ON time current is defined by the equation

I

ON

=

(

Ia

+

V

in

Rb

)

*

Ib

Vcomp

/

Ra

,

where I ON is the magnitude of the ON time current, Ia, Ib, Ra and Rb are constants, Vcomp is the amplified error signal, and V in is the monitored input voltage.

4. The controller of claim 1 , wherein the controller does not include terminals for monitoring individual currents through two or more inductors associated with the interleaved PFC converter.

5. An interleaved power factor correction (PFC) circuit comprising:

a rectifier circuit for converting an alternating current (AC) voltage to a rectified input voltage;

a first power factor correction (PFC) sub-circuit having a first inductor and a first switching device, the first inductor connected to store energy provided by the rectified input voltage when the first switching device is ON and to discharge stored energy to a direct current (DC) output when the first switching device is OFF;

a second power factor correction (PFC) sub-circuit connected in parallel with the first PFC sub-circuit and having a second inductor and a second switching device, the second inductor connected to store energy provided by the rectified input voltage when the second switching device is ON and to discharge stored energy to the DC output voltage when the second switching device is OFF; and

a controller that provides gate drive signals to the first switching device and the second switching device to define ON and OFF times of each switching device to ensure operation of the interleaved PFC converter in a discontinuous conduction mode (DCM) based on inputs that include a monitored input voltage, a monitored output voltage, a monitored sum of currents through the first and second PFC sub-circuits, and an amplified error signal that is related to the monitored output voltage, the controller provides frequency compression by relating the ON time of each switching device to the amplified error signal and the monitored input voltage, and the OFF time of each switch to the monitored input voltage, the monitored output voltage, and the ON time.

6. The interleaved PFC converter of claim 5 , wherein for each gate drive signal the controller includes:

a current source I ON having a magnitude related to the amplified error signal and the monitored input voltage;

a current source I OFF having a magnitude related to the rectified input voltage, the monitored output voltage, and the current source I ON ;

at least one capacitor;

a first comparator having a first input connected to a first voltage reference value and a second input connected to the capacitor, wherein the comparator generates a signal indicating when a capacitor voltage exceeds the voltage reference; and

wherein during a time required for the current source I ON to increase the capacitor voltage to a value greater than the voltage reference represents the ON time of the switching device and a time required for the current source I OFF to increase the capacitor voltage to a value greater than the voltage reference represents the OFF time of the switching device.

7. A method of controlling an interleaved power factor correction (PFC) converter by calculating an ON time of the PFC converter based on an amplified error signal and calculating an OFF time of the PFC converter based on a monitored input voltage, a monitored output voltage, the calculated ON time, and the amplified error signal, wherein the improvement comprises:

calculating the ON time of the PFC converter based in addition on the monitored input voltage to provide frequency compression of the interleaved PFC converter.

8. The method of claim 7 , wherein calculating the ON time of the PFC converter is defined by the equation

I

ON

=

K

Vcomp

+

V

in

Rb

,

where I ON is the magnitude of an ON time current source, K is a constant, Rb is a resistance value, Vcomp is the amplified error signal, and V in is the monitored input voltage.

9. The method of claim 7 , wherein calculating the ON time of the PFC converter is defined by the equation

I

ON

=

(

Ia

+

V

in

Rb

)

*

Ib

Vcomp

/

Ra

,

where I ON is the magnitude of an ON time current source, Ia and Ib are constant current sources, Ra and Rb are resistance values, Vcomp is the amplified error signal, and V in is the monitored input voltage.