Hardware transactional memory acceleration through multiple failure recovery

1. A method for executing instructions in a transactional-scout mode in a processor, comprising:

transactionally executing instructions in the processor from a protected section of program code;

entering the transactional-scout mode and speculatively executing subsequent instructions in the transactional-scout mode when the transactional execution of the protected section of program causes a transactional failure condition;

executing subsequent instructions in the transactional-scout mode until the transactional failure condition is resolved or until the transactional failure condition and one or more additional transactional failure conditions are resolved; and

responsive to the transactional failure condition being resolved, returning to a normal-execution mode to execute instructions from a fail PC,

wherein a COMMIT instruction indicates an end of the protected section of program code, and wherein executing subsequent instructions in the transactional-scout mode comprises:

executing the instructions in the protected section including the COMMIT instruction in the transactional-scout mode, but preventing any transactional results from being committed to an architectural state of the processor in response to executing the COMMIT instruction; and

continuing to execute instructions following the protected section in the transactional-scout mode until the transactional failure condition is resolved.

2. The method of claim 1 , wherein the method further comprises:

before encountering the end of the protected section of program code and responsive to determining that the transactional failure condition has been resolved, leaving the transactional-scout mode and returning to the normal-execution mode to execute instructions from the fail PC.

3. The method of claim 1 , wherein entering the transactional-scout mode comprises setting a transactional-failure indicator, wherein executing the COMMIT instruction while executing instructions in a transactional-execution mode or the transactional-scout mode involves:

checking a state of the transactional-failure indicator; and

when the transactional-failure indicator is set, executing the COMMIT instruction without committing any transactional results to the architectural state of the processor.

4. The method of claim 1 , wherein executing program code in the transactional-scout mode involves executing instructions to generate prefetches for cache lines and to update processor state, but not committing transactional-scout mode results to an architectural state of the processor.

5. An apparatus for executing instructions in a transactional-scout mode, comprising:

a processor, wherein the processor is configured to:

transactionally execute instructions from a protected section of program code;

responsive to encountering a transactional failure condition, enter the transactional-scout mode and speculatively execute subsequent instructions in the transactional-scout mode;

execute subsequent instructions in the transactional-scout mode until the transactional failure condition is resolved or until the transactional failure condition and one or more additional transactional failure conditions are resolved; and

responsive to the transactional failure condition being resolved, return to a normal-execution mode to execute instructions from a fail PC,

wherein a COMMIT instruction indicates an end of the protected section of program code, and wherein when executing subsequent instructions in the transactional-scout mode until the transactional failure condition is resolved, the processor is configured to:

execute the instructions in the protected section including the COMMIT instruction in the transactional-scout mode, but prevent any transactional results from being committed to an architectural state of the processor in response to executing the COMMIT instruction; and

continue to execute instructions following the protected section in the transactional-scout mode until the transactional failure condition is resolved.

6. The apparatus of claim 5 , wherein before encountering an end of the protected section of program code and responsive to determining that the transactional failure condition has been resolved, the processor is configured to leave the transactional-scout mode and return to the normal-execution mode to execute instructions from the fail PC.

7. The apparatus of claim 5 , wherein when entering the transactional-scout mode the processor is configured to set a transactional-failure indicator, wherein when executing a COMMIT instruction while executing instructions in a transactional-execution mode or the transactional-scout mode, the processor is further configured to:

check a state of the transactional-failure indicator; and

when the transactional-failure indicator is set, execute the COMMIT instruction without committing any transactional results to the architectural state of the processor.

8. The apparatus of claim 5 , wherein executing program code in the transactional-scout mode involves executing instructions to generate prefetches for cache lines and to update processor state, but not committing transactional-scout mode results to an architectural state of the processor.

9. A computer system for executing instructions in a transactional-scout mode, comprising:

a processor, wherein the processor is configured to:

transactionally execute instructions from a protected section of program code;

responsive to encountering a transactional failure condition, enter the transactional-scout mode and speculatively execute subsequent instructions in the transactional-scout mode;

execute subsequent instructions in the transactional-scout mode until the transactional failure condition is resolved or until the transactional failure condition and one or more additional transactional failure conditions are resolved; and

responsive to the transactional failure condition being resolved, return to a normal-execution mode to execute instructions from a fail PC; and

a memory coupled to the processor, wherein the memory stores instructions and data for the processor,

wherein a COMMIT instruction indicates an end of the protected section of program code, and wherein when executing subsequent instructions in the transactional-scout mode until the transactional failure condition is resolved, the processor is configured to:

execute the instructions in the protected section including the COMMIT instruction in the transactional-scout mode, but prevent any transactional results from being committed to an architectural state of the processor in response to executing the COMMIT instruction; and

continue to execute instructions following the protected section in the transactional-scout mode until the transactional failure condition is resolved.

10. The computer system of claim 9 , wherein before encountering an end of the protected section of program code and responsive to determining that the transactional failure condition has been resolved, the processor is configured to leave the transactional-scout mode and return to the normal-execution mode to execute instructions from the fail PC.

11. The computer system of claim 9 , wherein when entering the transactional-scout mode the processor is configured to set a transactional-failure indicator, wherein when executing a COMMIT instruction while executing instructions in a transactional-execution mode or the transactional-scout mode, the processor is further configured to:

check a state of the transactional-failure indicator; and

when the transactional-failure indicator is set, execute the COMMIT instruction without committing any transactional results to the architectural state of the processor.