Semiconductor integrated circuit device
View Patent ↗An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.
1. A semiconductor memory circuit comprising:
a plurality of memory cells;
a first bit line connected to one storage node of each of the plurality of memory cells,
a second bit line connected to another storage node of each of the plurality of memory cells, the respective another storage nodes having data complementary to that of the respective one storage nodes;
a first double gate transistor connected between the first bit line and a voltage supply line, the first double gate transistor including a first gate having a first gate electrode and a first gate insulating film, and a second gate having a second gate electrode and a second gate insulating film, a thickness of the second gate insulating film being larger than a thickness of the first gate insulating film, and
a second double gate transistor connected between the second bit line and the voltage supply line, the second double gate transistor including a third gate having a third gate electrode and a third gate insulating film, and a fourth gate having a fourth gate electrode and a fourth gate insulating film, a thickness of the fourth gate insulating film being larger than a thickness of the third gate insulating film,
wherein the first gate electrode is connected to the third gate electrode and the second gate electrode is connected to the fourth gate electrode,
wherein the semiconductor memory circuit is constructed such that:
the voltage supply line is supplied with a first potential;
in a first period, a common potential is simultaneously supplied to the first to fourth gate electrodes; and
in a second period, the first potential is commonly supplied to the first and third gate electrodes, and a second potential being different from the first potential is commonly supplied to the second and fourth gate electrodes.
2. The semiconductor memory circuit according to claim 1 ,
wherein the semiconductor memory circuit is SRAM.
3. The semiconductor memory circuit according to claim 1 ,
wherein the semiconductor memory circuit is constructed such that a gate leakage current flowing in the second period is less than a gate leakage current flowing in the first period.