Display substrate and display panel having the same
View Patent ↗A display substrate includes a pixel electrode and a photoalignment film. The pixel electrode is disposed on a base substrate. The pixel electrode includes a first sub-electrode, a second sub-electrode separated from the first sub-electrode, and a micro-slit pattern disposed on at least one of the first and second sub-electrodes. The photoalignment film is disposed on the pixel electrode to respectively divide the first and second sub-electrodes into a plurality of domains.
1. A display substrate, comprising:
a pixel electrode disposed on a base substrate and comprising a first sub-electrode, a second sub-electrode separated from the first sub-electrode, and a micro-slit pattern formed on at least one of the first sub-electrode and the second sub-electrode; and
a photoalignment film disposed on the pixel electrode and respectively dividing the first sub-electrode and the second sub-electrode into a plurality of domains.
2. The display substrate of claim 1 , wherein the micro-slit pattern is formed on at least one of the entire surface of the first sub-electrode and the entire surface of the second sub-electrode.
3. The display substrate of claim 1 , wherein the micro-slit pattern is formed on at least one of a portion of the first sub-electrode and a portion of the second sub-electrode.
4. The display substrate of claim 1 , wherein the pixel electrode further comprises a plurality of the micro-slit patterns comprising a plurality of micro-electrodes having inclination directions parallel with a longitudinal axis of the pixel electrode, and
wherein the inclination directions of the micro-electrodes in the domains are different from each other.
5. The display substrate of claim 4 , wherein the inclination directions of the micro-electrodes disposed in adjacent domains are orthogonal.
6. The display substrate of claim 5 , wherein the inclination directions of the micro-electrodes disposed in the domains opposite to each other are parallel.
7. The display substrate of claim 4 , wherein a width of the micro-electrode and a gap between adjacent micro-electrodes are each in the range of 3 μm to 4 μm.
8. The display substrate of claim 1 , further comprising:
a first transistor connected to a gate line extended in a first direction and a first data line extended in a second direction crossing the first direction, the first transistor to output a voltage transmitted from the first data line to the first sub-electrode; and
a second transistor connected to the gate line and a second data line adjacent to the first data line, the second transistor to output a voltage transmitted from the second data line to the second sub-electrode.
9. The display substrate of claim 8 , further comprising:
a color filter layer disposed between the base substrate and the pixel electrode; and
a light-blocking pattern disposed on the base substrate on which the data lines and the first transistor and the second transistor are formed.
10. A display panel, comprising:
a display substrate comprising:
a pixel electrode disposed on a base substrate and comprising a first sub-electrode, a second sub-electrode separated from the first sub-electrode, and a micro-slit pattern formed on at least one of the first sub-electrode and the second sub-electrode; and
a photoalignment film disposed on the pixel electrode and dividing the first sub-electrode and the second sub-electrode into a plurality of domains;
an opposite substrate coupled with the display substrate, the opposite substrate comprising a common electrode facing the pixel electrode; and
a liquid crystal layer disposed between the opposite substrate and the display substrate.
11. The display panel of claim 10 , wherein the micro-slit pattern is formed on at least one of the entire surface of the first sub-electrode and the entire surface of the second sub-electrode.
12. The display panel of claim 10 , wherein the micro-slit pattern is formed on at least one of a portion of the first sub-electrode and a portion of the second sub-electrode.
13. The display panel of claim 12 , wherein the micro-slit pattern is formed from an edge of the pixel electrode toward an inside of the pixel electrode, and
wherein the length of the micro-slit pattern is in the range of 6 μm to 25 μm.
14. The display panel of claim 10 , wherein the pixel electrode further comprises a plurality of the micro-slit patterns comprising a plurality of micro-electrodes having inclination directions forming an angle with a longitudinal axis of the pixel electrode, and
wherein the inclination angles of the micro-electrodes in the domains are different from each other.
15. The display panel of claim 14 , wherein the inclination directions of the micro-electrodes disposed in adjacent domains are orthogonal.
16. The display substrate of claim 15 , wherein the inclination directions of the micro-electrodes disposed in the domains opposite to each other are parallel.
17. The display panel of claim 10 , further comprising:
a first transistor connected to a gate line extended in a first direction and a first data line extended in a second direction crossing the first direction, the first transistor to output a voltage transmitted from the first data line to the first sub-electrode; and
a second transistor connected to the gate line and a second data line adjacent to the first data line, the second transistor to output a voltage transmitted from the second data line to the second sub-electrode.
18. The display panel of claim 17 , wherein the display substrate further comprises:
a color filter layer disposed between the base substrate and the pixel electrode; and
a light-blocking pattern disposed on the base substrate on which the data lines and the first transistor and the second transistor are formed.
19. The display panel of claim 17 , wherein the opposite substrate further comprises:
a base substrate;
a color filter layer disposed between the base substrate and the common electrode; and
a light-blocking pattern disposed on the base substrate.