Method for fabricating thin film transistors and array substrate including the same

1. A method for fabricating a thin film transistor array substrate, comprising:

providing a substrate and forming a semi-conductive on the substrate, wherein the substrate has a pixel area;

forming a patterned photoresist layer with a first thickness and a second thickness on the semi-conductive layer, including forming the patterned photoresist layer on the semi-conductive layer in the pixel area of the substrate, wherein the first thickness is larger than the second thickness, and wherein the patterned photoresist layer in the pixel area has the second thickness;

patterning the semi-conductive layer by using the patterned photoresist layer as a mask to form a patterned semi-conductive layer comprising a first patterned semi-conductive layer and a second patterned semi-conductive layer;

removing the second thickness of the patterned photoresist layer;

performing a first ion doping process on the patterned semi-conductive layer by using remaining part of the patterned photoresist layer as a mask to form a source/drain region in the second patterned semi-conductive layer;

removing the first thickness of the patterned photoresist layer on the second patterned semi-conductive layer; and

forming a dielectric layer and a gate on the patterned semi-conductive layer.

2. The method as claimed in claim 1 , wherein part of the second patterned semi-conductive layer is exposed after the second thickness of the patterned photoresist layer is removed.

3. The method as claimed in claim 1 , further comprising; performing a second ion doping process on the patterned semi-conductive layer by using the gate as a mask to form a source-drain region in the first patterned semi-conductive layer.

4. The method as claimed in claim 3 , wherein doping concentration of the second ions in the second ion doping process is less than doping concentration of first ions in the first ion doping process.

5. The method as claimed in claim 3 , further comprising a step between the first ion doping process and the second ion doping process, which comprises performing a channel doping process on the patterned semi-conductive layer to form a channel region in the second patterned semi-conductive layer.

6. The method as claimed in claim 5 , wherein doping concentration of ions in the channel doping process is less than doping concentration of first ions in the first ion doping process.

7. The method as claimed in claim 1 , wherein the step of forming the patterned semi-conductive layer comprises forming a third patterned semi-conductive layer by using the patterned photoresist layer as a mask.

8. The method as claimed in claim 7 , wherein the first ion doping process is further performed on the third patterned semi-conductive layer to use the doped third patterned semi-conductive layer as an electrode of a semiconductor capacitor in the pixel area.

9. The method as claimed in claim 1 , wherein the process for forming the patterned photoresist layer on the substrate comprises:

forming a photoresist layer on the substrate; and

patterning the photoresist layer by a half-tone mask to form the patterned photoresist layer with the first thickness and the second thickness.

10. The method as claimed in claim 1 , wherein the patterned photoresist layer corresponding to the first patterned semi-conductive layer has the first thickness and the patterned photoresist layer corresponding to the second patterned semi-conductive layer has the first thickness and the second thickness.